HYB39S256800CTL-8 Infineon Technologies, HYB39S256800CTL-8 Datasheet - Page 49

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HYB39S256800CTL-8

Manufacturer Part Number
HYB39S256800CTL-8
Description
Manufacturer
Infineon Technologies
Datasheet

Specifications of HYB39S256800CTL-8

Lead Free Status / Rohs Status
Not Compliant
Change List
INFINEON Technologies
27.1.2000
11.4.2000
14.4.2000
25.4.2000
28.6.2000
20.7.2000
8.8.2000
23.8.99
6.10.99
3.12.99
Clock suspend mode is added in the datasheet and the waveform drawings again.
page 17: “mode register set-up time” renamed to “Mode Register set to Active
confusion note 4 on page 8, removed, burst stop is supported for BL =2,4 & 8
some PC133 parameters changed according to INTELs PC133 specification
Power Down Exit with one clock beginning with DD3D designstep
Full page burst is functional beginning with designstep DD3A.
Implemented into the datasheet as optional (untested) feature
Note for availability of components with twr = 1 clock interlock
Waveform Drawing changed from SPT03910 to SPT03910_2
Waveform Drawing changed from SPT03923 to SPT03923_2
Waveform Drawing changed from SPT03925 to SPT03925_2
Waveform Drawing changed from SPT03927 to SPT03927_2
Waveform Drawing changed from SPT03911 to SPT03911_2
Clock Suspend Mode not supported anymore (Dr.Savignac)
Some ICC currents changed after measurement of first lots
ICC6 for Low Power Versions changed from 1.5 to 1.7 mA
Waveforms: chapters 11 & 12 deleted and renumbered
Clock suspend mode functional with DD3D designstep
Waveform Drawing SPT03925_2 trp arrow corrected
Datasheet changed from Target to Preliminary
Last minute changes requested by Mr. Lüken
Text change on page 16 (for clarification)
Preliminary datasheet changed to final
Mail from Ralf Schneider, April 12. 00
twr = 2 Clock on this design version
Tras interlock changed to 4 clocks
(Discussion with Hahn and Lüken)
Change request from Mr. Lüken:
Changes on pages 1, 8 & 15
page 16: note 4 for ICC1
First Rev.
21
delay”
HYB39S256400/800/160CT(L)
256MBit Synchronous DRAM
8.00

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