82V3255TFG IDT, Integrated Device Technology Inc, 82V3255TFG Datasheet - Page 61
82V3255TFG
Manufacturer Part Number
82V3255TFG
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.82V3255TFG.pdf
(132 pages)
Specifications of 82V3255TFG
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
64
Mounting
Surface Mount
Lead Free Status / Rohs Status
Compliant
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INTERRUPTS2_ENABLE_CNFG - Interrupt Control 2
INTERRUPTS3_ENABLE_CNFG - Interrupt Control 3
Programming Information
IDT82V3255
Address: 11H
Type: Read / Write
Default Value:00XXXXX0
Address: 12H
Type: Read / Write
Default Value: 00X0XXXX
EX_SYNC_ALARM
T0_OPERATING
5 - 1
3 - 0
Bit
Bit
7
6
0
7
6
5
4
_MODE
7
7
T0_OPERATING_MODE
EX_SYNC_ALARM
T0_MAIN_REF_FAILED
INPUT_TO_T4
T4_STS
IN3_CMOS
Name
T0_MAIN_REF_F
Name
-
-
-
T4_STS
AILED
6
6
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when an external sync alarm has
occurred, i.e., when the EX_SYNC_ALARM bit (b7, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T4 DPLL locking status
changes (from ‘locked’ to ‘unlocked’ or from ‘unlocked’ to ‘locked’), i.e., when the T4_STS bit (b6, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
Reserved.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when all the input clocks for T4 path
change to be unqualified, i.e., when the INPUT_TO_T4 bit (b4, 0FH) is ‘1’.
0: Disabled. (default)
1: Enabled.
Reserved.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 DPLL operating mode
switches, i.e., when the T0_OPERATING_MODE bit (b7, 0EH) is ‘1’.
0: Disabled. (default)
1: Enabled.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the T0 selected input clock
has failed; i.e., when the T0_MAIN_REF_FAILED bit (b6, 0EH) is ‘1’.
0: Disabled. (default)
1: Enabled.
Reserved.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity
changes (from ‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding IN3_CMOS bit (b0, 0EH) is ‘1’.
0: Disabled. (default)
1: Enabled.
5
-
5
-
INPUT_TO_T4
4
4
-
61
3
3
-
-
Description
Description
2
-
2
-
1
-
1
-
December 3, 2008
IN3_CMOS
0
0
WAN PLL
-
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