ISPLSI 2064VE-135LTN44I Lattice, ISPLSI 2064VE-135LTN44I Datasheet
ISPLSI 2064VE-135LTN44I
Specifications of ISPLSI 2064VE-135LTN44I
Related parts for ISPLSI 2064VE-135LTN44I
ISPLSI 2064VE-135LTN44I Summary of contents
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... Scan Testable. The ispLSI 2064VE offers non-volatile reprogrammability of the logic, as well as the intercon- nect, to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2064VE device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1…B7 (see Figure 1). There are a total of 16 GLBs in the ispLSI 2064VE device ...
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... Functional Block Diagram Figure 1. ispLSI 2064VE Functional Block Diagram (64-I/O and 32-I/O Versions) Input Bus Output Routing Pool (ORP) Megablock I I/O 2 I/O 3 I/O 4 I/O 5 Global Routing Pool A1 I/O 6 (GRP) I/O 7 I I/O 10 I/O 11 I/O 12 I I/O 15 TDI/IN 0 ...
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... Capacitance (TA=25°C, f=1.0 MHz) SYMBOL PARAMETER C Dedicated Input Capacitance 1 C I/O Capacitance 2 C Clock and Global Output Enable Capacitance 3 Erase Reprogram Specifications PARAMETER Erase/Reprogram Cycles Specifications ispLSI 2064VE 1 -0.5 to +5.4V PARAMETER Commercial T = 0° 70°C A Industrial T = -40° 85°C A TYPICAL MINIMUM 10000 3 MIN ...
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... Refer to the Power Consumption CC section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum Specifications ispLSI 2064VE Figure 2. Test Load GND to 3.0V ≤ 1.5 ns 10% to 90% 1.5V 1.5V ...
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... External Synchronous Clock Pulse Duration, Low wl 1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. Specifications ispLSI 2064VE Over Recommended Operating Conditions 1 DESCRIPTION 2 1 ...
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... External Synchronous Clock Pulse Duration, Low wl 1. Unless noted otherwise, all parameters use a GRP load of four, 20 PTXOR path, ORP and Y0 clock. 2. Standard 16-bit counter using GRP feedback. 3. Reference Switching Test Conditions section. Specifications ispLSI 2064VE Over Recommended Operating Conditions 1 DESCRIPTION 2 1 ...
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... Global Reset to GLB gr 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Specifications ispLSI 2064VE 1 Over Recommended Operating Conditions DESCRIPTION 3 ...
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... Global Reset to GLB gr 1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros. Specifications ispLSI 2064VE 1 Over Recommended Operating Conditions DESCRIPTION 3 ...
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... Clock (max) + Reg co + Output grp + ptck(max (#20 + #22 + #35) + (#31) + (#36 + #38) 6.3ns = (0.4 + 0.4 + 2.9) + (0.2) + (1.2 + 1.2) Note: Calculations are based on timing specifications for the ispLSI 2064VE-280L. Specifications ispLSI 2064VE GRP GLB Feedback Comb 4 PT Bypass #23 GRP Reg 4 PT Bypass #22 # XOR Delays #25, 26, 27 Control ...
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... Product Terms Figure 3. Typical Device Power Consumption vs fmax I CC can be estimated for the ispLSI 2064VE using the following equation (mA PTs * 0.67 Nets * Fmax * 0.0045) Where PTs = Number of Product Terms used in design ...
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... Boundary Scan state machine. (2) When BSCAN is high, it functions as a dedicated clock input. GND Ground (GND) VCC Vcc Connect I/O Input/Output pins – These are the general purpose I/O pins used by the logic array pins are not to be connected to any active signals, VCC or GND. Specifications ispLSI 2064VE Description Description 11 ...
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... 32-I/O Signal Locations — Specifications ispLSI 2064VE I/O Locations Signal caBGA I I I I I/O 12 I/O 13 I I/O 16 I/O 17 I/O 18 I I I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 I/O 32 I I/O 35 ...
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... Signal Configuration ispLSI 2064VE 100-Ball caBGA Signal Diagram (0.8mm Ball Pitch/10.0 x 10.0mm Body Size I/O I I/O I I/O I I/O I GOE F VCC 0 TCK/ G GND IN 3 I/O I I/O I I/O I NCs are not to be connected to any active signals, VCC or GND. Note: Ball A1 indicator dot on top side of package. ...
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... Pin Configuration ispLSI 2064VE 100-Pin TQFP Pinout Diagram (0.5mm Lead Pitch/14.0 x 14.0mm Body Size RESET 11 VCC 12 GOE 1 13 GND 14 BSCAN 15 TDI pins are not to be connected to any active signals, VCC or GND. Specifications ispLSI 2064VE ispLSI 2064VE ...
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... PLCC Pinout Diagram (0.05in Lead Pitch/0.65 x 0.65in Body Size) I/O 28 I/O 29 I/O 30 I/O 31 GOE1/Y0 VCC BSCAN TDI/IN 0 I/O 0 I/O 1 I/O 2 Pin Configuration ispLSI 2064VE 44-Pin TQFP Pinout Diagram (0.8mm Lead Pitch/10.0 x 10.0mm Body Size) I/O 28 I/O 29 I/O 30 I/O 31 GOE1/Y0 VCC BSCAN TDI/IN 0 I/O 0 I/O 1 I/O 2 Specifications ispLSI 2064VE ...
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... Part Number Description ispLSI 2064VE XXX X XXXXX Device Family Device Number Speed f 280 = 280 MHz max f 200 = 200 MHz max f 135 = 135 MHz max f 100 = 100 MHz max ispLSI 2064VE Ordering Information Conventional Packaging FAMILY fmax (MHz) tpd (ns) 280 3.5 280 3 ...
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... INDUSTRIAL I/Os ORDERING NUMBER 64 ispLSI 2064VE-135LTN100I 32 ispLSI 2064VE-135LTN44I 17 PACKAGE Lead-Free 100-Pin TQFP Lead-Free 44-Pin TQFP Lead-Free 100-Pin TQFP Lead-Free 44-Pin TQFP Lead-Free 100-Pin TQFP Lead-Free 44-Pin TQFP Lead-Free 100-Pin TQFP Lead-Free 44-Pin TQFP PACKAGE Lead-Free 100-Pin TQFP ...