SI5010-B-GMR Silicon Laboratories Inc, SI5010-B-GMR Datasheet
SI5010-B-GMR
Specifications of SI5010-B-GMR
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SI5010-B-GMR Summary of contents
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... SONET/SDH/ATM routers Add/drop multiplexers Digital cross connects Board level serial links Description The Si5010 is a fully-integrated low-power clock and data recovery (CDR) IC designed for high-speed serial communication systems. It extracts timing information and data from a serial input at OC-12/3 or STM-4/1 data ® rates. DSPLL ...
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... Si5010 2 Rev. 1.4 ...
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... PLL Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.7. Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.8. Device Grounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.9. Bias Generation Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4.10. Differential Input Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4.11. Differential Output Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5. Pin Descriptions: Si5010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7. Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 8. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 9. 4x4 mm 20L QFN Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Contact Information ...
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... Si5010 1. Detailed Block Diagram DIN+ DIN+ Phase Phase Phase Detector Detector Detector DIN– REFCLK+ REFCLK+ REFCLK– RATESEL REXT Bias Bias Bias G eneration G eneration G eneration 4 CLK A/D VCO DSP Divider n Lock Detector Calibration Rev. 1.4 DOUT+ Retim e Retim e Retim e DOUT– ...
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... All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. 2. The Si5010 specifications are guaranteed when using the recommended application circuit (including component tolerance) shown in "3. Typical Application Schematic" on page 9. ...
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... Si5010 Table 2. DC Characteristics (V = 2.5 V ±5 –40°C to 85° Parameter Supply Current OC-12 OC-3 Power Dissipation OC-12 OC-3 Common Mode Input Voltage (DIN, REFCLK) Single Ended Input Voltage (DIN, REFCLK) Differential Input Voltage Swing* (DIN, REFCLK) Input Impedance (DIN, REFCLK) ...
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... OC-12 Mode BW OC-3 Mode J f < 2 MHz P T After falling edge of AQ PWRDN/CAL From the return of valid data C DUTY C TOL LOL LOCK Rev. 1.4 Si5010 Min Typ Max Unit 150 — 666 MHz — 80 110 ps 835 880 930 ps 4040 4090 4140 ps — ...
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... Si5010 Table 5. Absolute Maximum Ratings Parameter DC Supply Voltage LVTTL Input Voltage Differential Input Voltages Maximum Current any output PIN Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pf, 1.5 kΩ) Note: Permanent device damage may occur if the above absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet ...
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... Typical Application Schematic DIN+ High-Speed Serial Input DIN– System REFCLK+ Reference REFCLK– Clock LVTTL Control Inputs Loss-of-Lock Indicator 2 DOUT+ DOUT– Si5010 CLKOUT+ CLKOUT– 0.1 μF 10 kΩ VDD (1%) 2200 Rev. 1.4 Si5010 Recovered Data Recovered Clock 9 ...
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... When REFCLK is absent, the LOL alarm will always be asserted when it has been determined that no activity exists on REFCLK, indicating the lock status of the PLL is unknown. Additionally, the Si5010 uses the reference clock to center the VCO operating frequency so that clock and data can be recovered from the input data stream. The VCO operates at an integer multiple of the REFCLK frequency. (See “ ...
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... Note: LOL is not asserted when the device is in the power- down state. 4.8. Device Grounding The Si5010 uses the GND pad on the bottom of the 20-pin QFN package for device ground. This pad should be connected directly to the analog supply ground. See Figures 10 and 11 for the ground (GND) pad location. ...
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... Si5010 4.10. Differential Input Circuitry The Si5010 provides differential inputs for both the high-speed data (DIN) and the reference clock (REFCLK) inputs. An example termination for these inputs is shown in Figure 6. In applications where direct dc coupling is possible, the 0.1 µF capacitors may be omitted. The DIN and REFCLK input amplifiers require an input signal with a minimum differential peak-to-peak voltage listed in Table 2 on page 6 ...
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... Differential Output Circuitry The Si5010 utilizes a current mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data (DOUT). An example of output termination with ac coupling is shown in Figure 9. In applications in which direct dc coupling is possible, the 0.1 µF capacitors may be omitted. The differential peak-to-peak voltage swing of the CML architecture is listed in Table 2 on page 6. 100 Ξ ...
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... VDD Top View Figure 10. Si5010 Pin Configuration Table 8. Si5010 Pin Descriptions I/O Signal Level External Bias Resistor. This resistor is used by onboard circuitry to estab- lish bias currents within the device. This pin must be connected to GND through a 10 kΩ (1%) resis- tor. Supply Voltage. ...
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... Table 8. Si5010 Pin Descriptions (Continued) Pin # Pin Name I/O 12 DOUT– DOUT+ 15 PWRDN/CAL I 16 CLKOUT– CLKOUT+ 19 RATESEL Signal Level Description Differential Data Output. CML The data output signal is a retimed version of the data recovered from the signal present on DIN phase aligned with CLKOUT and is updated on the rising edge of CLKOUT ...
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... Add an “R” at the end of the device to denote tape and reel option; 2500 quantity per reel. 3. These devices use a NiPdAu pre-plated finish on the leads that is fully RoHS6 compliant while being fully compatible with both leaded and lead-free card assembly processes. 7. Top Mark Part Number Si5010-B-GM 16 Voltage Pb-Free 2.5 ...
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... Package Outline Figure 11 illustrates the package details for the Si5010. Table 9 lists the values for the dimensions shown in the illustration. Figure 11. 20-pin Quad Flat No-Lead (QFN) Symbol Millimeters Min Nom A 0.80 0.85 A1 0.00 0.02 b 0.18 0.25 c — — D 4.00 BSC D2 1.95 2 ...
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... Si5010 20L QFN Recommended PCB Layout See Note 8 Symbol A Pad Row/Column Width/Length D Thermal Pad Width/Height e Pad Pitch G Pad Row/Column Separation R Pad Radius X Pad Width Y Pad Length Z Pad Row/Column Extents Notes: 1. All dimensions listed are in millimeters (mm). 2. The perimeter pads are to be Non-Solder Mask Defined (NSMD). Solder mask openings should be designed to leave 60-75 mm separation between solder mask and pad metal, all the way around the pad ...
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... L OCUMENT HANGE IST Revision 1.0 to Revision 1.1 Added "7. Top Mark" on page 16. Updated “8. Package Outline: Si5010-BM” on page 17. Added "9. 4x4 mm 20L QFN Recommended PCB Layout" on page 18. Revision 1.1 to Revision 1.2 Made minor note corrections to "9. 4x4 mm 20L QFN Recommended PCB Layout" on page 18. ...
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... Si5010 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 7801 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: HighSpeed@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...