ATF1504AS-10JC84 Atmel, ATF1504AS-10JC84 Datasheet
ATF1504AS-10JC84
Specifications of ATF1504AS-10JC84
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ATF1504AS-10JC84 Summary of contents
Page 1
... Pull-up Option on JTAG Pins TMS and TDI • Advanced Power Management Features – Edge-controlled Power-down “L” – Individual Macrocell Power Option – Disable ITD on Global Clocks, Inputs and I/O High- performance Complex Programmable Logic Device ATF1504AS ATF1504ASL Rev. 0950N–PLD–07/02 1 ...
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... PLCC Top View I/O 10 VCCIO 11 I/O/TD1 12 I/O 13 I/O 14 I/O 15 GND 16 I/O/PD1 17 I/O 18 I/O/TMS 19 I/O 20 VCCIO 21 I/O 22 I/O 23 I/O 24 I/O 25 GND 26 ATF1504AS(L) 2 TDI/I/O 33 I/O 32 I/O/TDO 31 I/O GND 30 I/O PD1/I/O 29 VCC I/O/TMS 28 I/O 27 I/O 26 I/O/TCK VCC 25 I/O 24 GND 23 I/O 60 I/O I I/O VCCIO ...
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... I/O I/O/TMS 15 66 I/O I I/O I I/O/TCK VCCIO 18 63 I/O I I/O I GND I I I I/O 53 VCCIO ATF1504AS(L) 100-lead TQFP Top View 75 I/O 74 GND 73 I/O/TDO I I/O 68 I/O 67 I/O 66 VCCIO 65 I/O 64 I/O 63 I/O 62 I/O/TCK 61 I/O 60 I/O 59 GND 58 I/O 57 I I/O 51 VCCIO 3 ...
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... SSI, MSI, LSI and classic PLDs. The ATF1504AS’s enhanced routing switch matrices increase usable gate count and the odds of successful pin-locked design modifications. The ATF1504AS has bi-directional I/O pins and four dedicated input pins, depending on the type of device package selected. Each dedicated pin can also serve as a global control signal, register clock, register reset or output enable ...
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... Unused product terms are automatically disabled by the compiler to decrease power consumption. A security fuse, when programmed, protects the contents of the ATF1504AS. Two bytes (16 bits) of User Signature are accessible to the user for pur- poses such as storing project name, part number, revision or date. The User Signature is accessible regardless of the state of the security fuse ...
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... Product Terms and Select Each ATF1504AS macrocell has five product terms. Each product term receives as its Mux possible inputs all signals from both the global bus and regional bus. The product term select multiplexer (PTMUX) allocates the five product terms as needed to the macrocell logic gates and control signals. The PTMUX programming is determined by the design compiler, which selects the optimum macrocell configuration ...
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... The foldback is an inverse polarity of one of the macrocell’s product terms. The sixteen foldback terms in each region allow generation of high fan-in sum terms (up to sixteen product terms) with a nominal additional delay. Figure 1. ATF1504AS Macrocell 0950N–PLD–07/02 ATF1504AS(L) ...
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... Programmable Pin- The ATF1504AS offers the option of programming all input and I/O pins so that pin- keeper circuits can be utilized. When any pin is driven high or low and then subse- keeper Option for quently left floating, it will stay at that previous high- or low-level. This circuitry prevents ...
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... AC parameters, which include the data paths t The ATF1504AS macrocell also has an option whereby the power can be reduced on a per macrocell basis. By enabling this power-down option, macrocells that are not used in an application can be turned-down, thereby reducing the overall power consumption of the device ...
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... I/O pins to be used for logic. Contact your local Atmel representatives or Atmel PLD applications for details. ISP Programming The ATF1504AS has a special feature that locks the device and prevents the inputs and I/O from driving if the programming process is interrupted for any reason. The inputs Protection and I/O default to high-Z state during such a condition ...
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... Ind. CCIO OL Com MIN 0.1 mA Ind MIN -4.0 mA CCIO OH Typ Max Units ATF1504AS(L) Commercial Industrial 0°C - 70°C -40°C - 85°C 5V ± ± 10% 3.0V - 3.6V 3.0V - 3.6V Min Typ Max -2 - -40 40 105 130 105 4.75 5.25 4.5 5.5 3.0 3.6 -0.3 0.8 2 ...
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... Minimum Array Clock Period ACNT Maximum Internal Array f ACNT Clock Frequency ATF1504AS(L) 12 *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any ...
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... OD3 3.3V pF) CCIO L Note: See ordering information for valid part numbers. Timing Model 0950N–PLD–07/02 -7 -10 -15 Min Max Min Max Min 166.7 125 100 0.5 0.5 0.5 0 0.8 0 1.5 2.5 2.0 5 5.5 ATF1504AS(L) -20 -25 Max Min Max Min Max 83 1 Units ...
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... Reduced-power Adder RPA Notes: 1. See ordering information for valid part numbers. 2. The t parameter must be added to the t RPA power mode. Input Test Waveforms and Measurement Levels 1.5 ns typical R F ATF1504AS( -10 -15 Min Max Min Max Min Max 4.0 5.0 4.5 5.5 9 ...
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... Power-down Mode The ATF1504AS includes an optional pin-controlled power-down feature. When this mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the device supply current is reduced to less than 10 mA. During power-down, all output data and internal logic states are latched internally and held ...
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... I/O pins and macrocells are shown below. BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins) Note: The ATF1504AS has pull-up option on TMS and TDI pins. This feature is selected as a design option. ATF1504AS(L) 16 0950N–PLD–07/02 ...
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... BSC Configuration for Macrocell OEJ OUTJ 0950N–PLD–07/02 Pin BSC 0 Pin 1 Clock TDI Shift TDO Capture Update DR DR TDI Clock Shift Macrocell BSC ATF1504AS(L) TDO D Q Capture Pin 1 Mode 17 ...
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... PCI Compliance The ATF1504AS also supports the growing need in the industry to support the new Peripheral Component Interconnect (PCI) interface standard in PCI-based designs and specifications. The PCI interface calls for high current drivers, which are much larger than the traditional TTL drivers. In general, PLDs and FPGAs parallel outputs to support the high current load required by the PCI interface ...
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... OUT ≤ < V -25+( 0.4V to 2.4V load 0.5 2.4V to 0.4V load 0.5 - 5.25 2.45) for V > V > 3.1V. OUT CC OUT * (4 for 0V < V < 0.71V. OUT OUT ATF1504AS(L) Min Max 4.75 5.25 2 0.5 CC -0.5 0.8 70 -70 2.4 0. Max - 1.4)/0.024 Equation A -142 /0 ...
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... ATF1504AS Dedicated Pinouts 44-lead Dedicated Pin TQFP INPUT/OE2/GCLK2 40 INPUT/GCLR 39 INPUT/OE1 38 INPUT/GCLK1 37 I/O /GCLK3 35 I/O/PD (1, I/O/TDI (JTAG) 1 I/O/TMS (JTAG) 7 I/O/TCK (JTAG) 26 I/O/TDO (JTAG) 32 GND 4, 16, 24 17, 29, 41 CCINT V – CCIO N/C – Signal Pins 36 # User I/O Pins 32 OE (1, 2) Global OE Pins GCLR ...
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... ATF1504AS I/O Pinouts 44- 44- 68- lead lead lead MC PLC PLCC TQFP PLCC – – – PD1 – – – – – TDI 9 A – – – – – – – – – – – – – – – – – – – ...
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... FREQUENCY (MHz) OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE (VOH = 2.4V 25°C) A 0.0 -10.0 -20.0 -30.0 -40.0 -50.0 -60.0 4.50 4.75 5.00 SUPPLY VOLTAGE (V) ATF1504AS(L) 22 5.25 5.50 5.25 5.50 = 25°C) A 80.00 100.00 5.25 5.50 SUPPLY CURRENT VS. SUPPLY VOLTAGE PIN-CONTROLLED POWER-DOWN MODE (T = 25° ...
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... A 5.3 5.5 3.5 4.0 4.5 5.0 3.50 4.00 4.50 5.00 ATF1504AS(L) NORMALIZED TPD VS. TEMPERATURE (V = 5.0V) CC 0.0 25.0 TEMPERATURE (C) NORMALIZED TCO VS. SUPPLY VOLTAGE (T = 25°C) A 1.2 1.1 1.0 0.9 0.8 4.5 4.8 5.0 5 ...
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... NORMALIZED TCO VS.TEMPERATURE (V CC 1.2 1.1 1.0 0.9 0.8 -40.0 0.0 25.0 TEMPERATURE (C) NORMALIZED TSU VS. TEMPERATURE (V = 5.0V) CC 1.2 1.1 1.0 0.9 0.8 -40.0 0.0 25.0 TEMPERATURE (C) ATF1504AS( 5.0V) 75.0 75.0 0950N–PLD–07/02 ...
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... ATF1504AS Ordering Information CO1 MAX (ns) (ns) (MHz) 7.5 4.5 166 125 10 5 125 15 8 100 15 8 100 Using “C” Product for Industrial To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device (7 ns “ ...
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... ATF1504ASL Ordering Information CO1 MAX (ns) (ns) (MHz 83 Using “C” Product for Industrial To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device (7 ns “C” “I”) and de-rate power by 30%. ...
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... Orchard Parkway San Jose, CA 95131 R 0950N–PLD–07/ TITLE 44A, 44-lead Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) ATF1504AS(L) A COMMON DIMENSIONS (Unit of Measure = mm) MIN SYMBOL NOM MAX NOTE A – – 1.20 A1 0.05 – ...
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... Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. TITLE 2325 Orchard Parkway San Jose, CA 95131 R ATF1504AS(L) 28 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER ...
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... Lead coplanarity is 0.004" (0.102 mm) maximum. TITLE 2325 Orchard Parkway San Jose, CA 95131 R 0950N–PLD–07/02 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 68J, 68-lead, Plastic J-leaded Chip Carrier (PLCC) ATF1504AS(L) 0.318(0.0125) 0.191(0.0075) D2/ COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM NOTE A 4 ...
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... Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. TITLE 2325 Orchard Parkway San Jose, CA 95131 R ATF1504AS(L) 30 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER ...
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... PIN 1 14.12 (0.556) 13.90 (0.547) 0º~7º 1.03 (0.041) 0.73 (0.029) Plastic Quad Flat Package (PQFP) ATF1504AS(L) 20.10 (0.791) 19.90 (0.783) 23.45 (0.923) 22.95 (0.904) 3.40 (0.134) MAX 0.50 (0.020) 0.25 (0.010) 04/11/2001 DRAWING NO. ...
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... This package conforms to JEDEC reference MS-026, Variation AED. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.08 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R ATF1504AS( ...
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... No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ...