EPM7064SLI44-7N Altera, EPM7064SLI44-7N Datasheet - Page 43

IC MAX 7000 CPLD 64 44-PLCC

EPM7064SLI44-7N

Manufacturer Part Number
EPM7064SLI44-7N
Description
IC MAX 7000 CPLD 64 44-PLCC
Manufacturer
Altera
Series
MAX® 7000r
Datasheet

Specifications of EPM7064SLI44-7N

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
7.5ns
Voltage Supply - Internal
4.5 V ~ 5.5 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
36
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
44-PLCC
Voltage
5V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-2017
EPM7064SLI44-7N

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Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Altera Corporation
t
t
t
t
t
t
t
t
t
t
t
Symbol
FSU
FH
RD
COMB
IC
EN
GLOB
PRE
CLR
PIA
LPA
Table 30. EPM7064S Internal Timing Parameters (Part 2 of 2)
These values are specified under the recommended operating conditions shown in
information on switching waveforms.
This minimum pulse width for preset and clear applies for both global clear and array controls. The t
must be added to this minimum width if the clear or reset signal incorporates the t
path.
This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This
parameter applies for both global and array clocking.
These parameters are measured with a 16-bit loadable, enabled, up/down counter programmed into each LAB.
The f
Operating conditions: V
For EPM7064S-5, EPM7064S-6, EPM7128S-6, EPM7160S-6, EPM7160S-7, EPM7192S-7, and EPM7256S-7 devices,
these values are specified for a PIA fan-out of one LAB (16 macrocells). For each additional LAB fan-out in these
devices, add an additional 0.1 ns to the PIA timing value.
The t
running in the low-power mode.
LPA
MAX
Register setup time of fast
input
Register hold time of fast
input
Register delay
Combinatorial delay
Array clock delay
Register enable time
Global control delay
Register preset time
Register clear time
PIA delay
Low-power adder
parameter must be added to the t
values represent the highest frequency for pipelined data.
Parameter
CCIO
= 3.3 V ± 10% for commercial and industrial use.
(7)
(8)
Conditions
LAD
, t
LAC
MAX 7000 Programmable Logic Device Family Data Sheet
, t
Min Max Min Max Min Max Min Max
IC
1.9
0.6
, t
-5
EN
12.0
, t
1.2
1.6
1.1
0.9
2.7
2.6
2.0
2.0
SEXP
, t
ACL
1.8
0.7
Note (1)
-6
, and t
Speed Grade
11.0
1.6
1.0
3.3
3.2
1.9
2.4
2.4
1.3
CPPW
Table
3.0
0.5
LAD
parameters for macrocells
-7
parameter into the signal
14. See
10.0
1.0
3.0
1.0
1.0
1.0
3.0
2.0
2.0
Figure 13
3.0
0.5
-10
LPA
11.0
parameter
2.0
2.0
5.0
5.0
1.0
3.0
3.0
1.0
for more
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
43

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