XC2C64A-7CPG56C Xilinx Inc, XC2C64A-7CPG56C Datasheet - Page 14

• Manufacturer Part Number: XC2C64A-7CPG56C
• Description: IC CR-II CPLD 64MCELL 56-BGA
• Manufacturer: Xilinx Inc
• Series: CoolRunner IIr

Specifications of XC2C64A-7CPG56C

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.7ns
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Logic Elements/blocks: 4
• Number Of Macrocells: 64
• Number Of Gates: 1500
• Number Of I /o: 45
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-CSBGA
• Features: Programmable
• Voltage: 1.8V
• Memory Type: CMOS
• For Use With: 122-1536 - KIT STARTER SPARTAN-3E122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1408

CoolRunner-II CPLD Family
Absolute Maximum Ratings
Quality and Reliability Parameters
Warranty Disclaimer
THESE PRODUCTS ARE SUBJECT TO THE TERMS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED
AT http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF THE
PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE
THEN-CURRENT XILINX DATA SHEET FOR THE PRODUCTS. PRODUCTS ARE NOT DESIGNED TO BE FAIL-SAFE
AND ARE NOT WARRANTED FOR USE IN APPLICATIONS THAT POSE A RISK OF PHYSICAL HARM OR LOSS OF
LIFE. USE OF PRODUCTS IN SUCH APPLICATIONS IS FULLY AT THE RISK OF CUSTOMER SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
Further Reading
Application Notes
http://www.xilinx.com/support/documenta-
tion/application_notes/xapp784.pdf
(Bulletproof Design Practices)
http://www.xilinx.com/support/documentation/application_no
tes/xapp375.pdf
http://www.xilinx.com/support/documentation/application_no
tes/xapp376.pdf
14
Notes:
1.
2.
3.
4.
Notes:
1.
Symbol
Stresses above those listed might cause malfunction or permanent damage to the device. This is a stress rating only. Functional
operation at these or any other condition above those indicated in the operational and programming specification is not implied.
The chip supply voltage should rise monotonically.
Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins might undershoot to –2.0V or overshoot to 4.5 V, provided this overshoot or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA. The I/O voltage can never exceed 4.0V.
For soldering guidelines and thermal considerations, see the
packages, see XAPP427.
ESD is measured to 2000V using the human body model. Pins exposed to this limit can incur additional leakage current to
a maximum of 10 μA when driven to 3.9V.
V
T
N
ESD
DR
PE
Symbol
V
T
T
V
CC
T
STR
J
I
(3)
A
(4)
(2)
(Timing Model)
(Logic Engine)
Data retention
Program/erase cycles (Endurance)
Electrostatic discharge(1)
Supply voltage relative to GND
Input voltage relative to GND
Ambient Temperature (C-grade)
Ambient Temperature (I-grade)
Maximum junction temperature
Storage temperature
Parameter
Parameter
www.xilinx.com
Device Packaging
(1)
http://www.xilinx.com/support/documenta-
tion/application_notes/xapp317.pdf
(Power Evaluation Equation for CoolRunner-II CPLDs)
http://www.xilinx.com/support/documentation/application_no
tes/xapp377.pdf
http://www.xilinx.com/support/documentation/application_no
tes/xapp378.pdf
http://www.xilinx.com/support/documentation/application_no
tes/xapp379.pdf
http://www.xilinx.com/support/documentation/application_no
tes/xapp380.pdf
information on the Xilinx website. For Pb-free
1,000
2,000
Min
20
(Low Power Design)
(Advanced Features)
(High Speed Design)
(Cross Point Switch)
–0.5
–0.5
DS090 (v3.1) September 11, 2008
Min.
–40
–40
–65
Max
0
-
-
-
Product Specification
Cycles
Max.
150
150
Units
Years
Volts
2.0
4.0
70
85
Unit
°C
°C
°C
°C
V
V
R