XC2C64A-7CPG56C Xilinx Inc, XC2C64A-7CPG56C Datasheet - Page 4

• Manufacturer Part Number: XC2C64A-7CPG56C
• Description: IC CR-II CPLD 64MCELL 56-BGA
• Manufacturer: Xilinx Inc
• Series: CoolRunner IIr

Specifications of XC2C64A-7CPG56C

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.7ns
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Logic Elements/blocks: 4
• Number Of Macrocells: 64
• Number Of Gates: 1500
• Number Of I /o: 45
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-CSBGA
• Features: Programmable
• Voltage: 1.8V
• Memory Type: CMOS
• For Use With: 122-1536 - KIT STARTER SPARTAN-3E122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1408

CoolRunner-II CPLD Family
path. The BSC and ISP block has the JTAG controller and
In-System Programming Circuits.
Function Block
The CoolRunner-II CPLD FBs contain 16 macrocells, with
40 entry sites for signals to arrive for logic creation and con-
nection. The internal logic engine is a 56 product term PLA.
All FBs, regardless of the number contained in the device,
are identical. For a high-level view of the FB, see
At the high level, the product terms (p-terms) reside in a
programmable logic array (PLA). This structure is extremely
4
Figure 2: CoolRunner-II CPLD Function Block
I/O Pin
I/O Pin
I/O Pin
JTAG
40
Set/Reset
PLA
BSC and ISP
Global
16
16
MC16
MC1
MC2
Global
Clocks
MC16
MC1
MC2
3
16
Direct Inputs
DS090_02_101001
Figure 1: CoolRunner-II CPLD Architecture
Function
Block 1
PLA
Out
To AIM
16 FB
Figure
40
Clock and Control Signals
www.xilinx.com
2.
BSC Path
AIM
flexible, and very robust when compared to fixed or cas-
caded product term FBs.
Classic CPLDs typically have a few product terms available
for a high-speed path to a given macrocell. They rely on
capturing unused p-terms from neighboring macrocells to
expand their product term tally, when needed. The result of
this architecture is a variable timing model and the possibil-
ity of stranding unusable logic within the FB.
The PLA is different — and better. First, any product term
can be attached to any OR gate inside the FB macrocell(s).
Second, any logic function can have as many p-terms as
needed attached to it within the FB, to an upper limit of 56.
Third, product terms can be re-used at multiple macrocell
OR functions so that within a FB, a particular logical product
need only be created once, but can be re-used up to 16
times within the FB. Naturally, this plays well with the fitting
software, which identifies product terms that can be shared.
The software places as many of those functions as it can
into FBs, so it happens for free. There is no need to force
macrocell functions to be adjacent or any other restriction
save residing in the same FB, which is handled by the soft-
ware. Functions need not share a common clock, common
set/reset, or common output enable to take full advantage of
the PLA. Also, every product term arrives with the same
time delay incurred. There are no cascade time adders for
putting more product terms in the FB. When the FB product
term budget is reached, there is a small interconnect timing
penalty to route signals to another FB to continue creating
logic. Xilinx design software handles all this automatically.
16 FB
40
Function
Block n
PLA
Direct Inputs
MC16
MC1
MC2
DS090 (v3.1) September 11, 2008
16
16
Product Specification
DS090_01_121201
I/O Pin
I/O Pin
I/O Pin
R