XC2C64A-7CPG56C Xilinx Inc, XC2C64A-7CPG56C Datasheet - Page 5

• Manufacturer Part Number: XC2C64A-7CPG56C
• Description: IC CR-II CPLD 64MCELL 56-BGA
• Manufacturer: Xilinx Inc
• Series: CoolRunner IIr

Specifications of XC2C64A-7CPG56C

• Programmable Type: In System Programmable
• Delay Time Tpd(1) Max: 6.7ns
• Voltage Supply - Internal: 1.7 V ~ 1.9 V
• Number Of Logic Elements/blocks: 4
• Number Of Macrocells: 64
• Number Of Gates: 1500
• Number Of I /o: 45
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-CSBGA
• Features: Programmable
• Voltage: 1.8V
• Memory Type: CMOS
• For Use With: 122-1536 - KIT STARTER SPARTAN-3E122-1532 - KIT DEVELOPMENT SPARTAN 3ADSP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Logic Elements/cells: -
• Other names: 122-1408

Macrocell
The CoolRunner-II CPLD macrocell is extremely efficient
and streamlined for logic creation. Users can develop sum
of product (SOP) logic expressions that comprise up to 40
inputs and span 56 product terms within a single function
block. The macrocell can further combine the SOP expres-
sion into an XOR gate with another single p-term expres-
sion. The resulting logic expression’s polarity is also
selectable. As well, the logic function can be pure combina-
torial or registered, with the storage element operating
selectably as a D or T flip-flop, or transparent latch. Avail-
able at each macrocell are independent selections of global,
function block level or local p-term derived clocks, sets,
When configured as a D-type flip-flop, each macrocell has
an optional clock enable signal permitting state hold while a
clock runs freely. Note that Control Terms (CT) are available
to be shared for key functions within the FB, and are gener-
ally used whenever the exact same logic function would be
repeatedly created at multiple macrocells. The CT product
terms are available for FB clocking (CTC), FB asynchro-
nous set (CTS), FB asynchronous reset (CTR), and FB out-
put enable (CTE).
Any macrocell flip-flop can be configured as an input regis-
ter or latch, which takes in the signal from the macrocell’s
I/O pin, and directly drives the AIM. The macrocell combina-
DS090 (v3.1) September 11, 2008
Product Specification
R
From AIM
40
49 P-terms
CTC
PTC
4 P-terms
PLA OR Term
PTC
PTA
PTB
GND
V
GCK0
GCK1
GCK2
CC
To PTA, PTB, PTC of
other macrocells
CTC, CTR,
CTS, CTE
Figure 3: CoolRunner-II CPLD Macrocell
Direct Input
I/O Block
www.xilinx.com
from
GND
GND
GSR
GSR
CTR
CTS
PTA
PTA
resets, and output enables. Each macrocell flip-flop is con-
figurable for either single edge or DualEDGE clocking, pro-
viding either double data rate capability or the ability to
distribute a slower clock (thereby saving power). For single
edge clocking or latching, either clock polarity can be
selected per macrocell. CoolRunner-II CPLD macrocell
details are shown in
dard logic symbols are used except the trapezoidal multi-
plexers have input selection from statically programmed
configuration select lines (not shown). Xilinx application
note XAPP376 gives a detailed explanation of how logic is
created in the CoolRunner-II CPLD family.
tional functionality is retained for use as a buried logic node
if needed. F
a T flip-flop can reliably toggle.
Advanced Interconnect Matrix (AIM)
The Advanced Interconnect Matrix is a highly connected
low power rapid switch. The AIM is directed by the software
to deliver up to a set of 40 signals to each FB for the cre-
ation of logic. Results from all FB macrocells, as well as, all
pin inputs circulate back through the AIM for additional con-
nection available to all other FBs as dictated by the design
PTC
D/T
CE
CK
Toggle
FIF
Latch
DualEDGE
R
S
is the maximum clock frequency to which
Q
Feedback
Figure
to AIM
3. Note that in
CoolRunner-II CPLD Family
To I/O Block
DS090_03_121201
Figure
4, stan-
5