XC9572XL-10TQG100I Xilinx Inc, XC9572XL-10TQG100I Datasheet - Page 14

• Manufacturer Part Number: XC9572XL-10TQG100I
• Description: IC CPLD 1.6K 72MCELL 100-TQFP
• Manufacturer: Xilinx Inc
• Series: XC9500XLr

Specifications of XC9572XL-10TQG100I

• Programmable Type: In System Programmable (min 10K program/erase cycles)
• Delay Time Tpd(1) Max: 10.0ns
• Voltage Supply - Internal: 3 V ~ 3.6 V
• Number Of Logic Elements/blocks: 4
• Number Of Macrocells: 72
• Number Of Gates: 1600
• Number Of I /o: 72
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Voltage: 3.3V
• Memory Type: FLASH
• For Use With: 122-1512 - KIT DESIGN CPLD W/BATT HOLDER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Number Of Logic Elements/cells: -
• Other names: 122-1387

instructions are supported in each device. Additional
instructions are included for in-system programming opera-
tions.
Design Security
XC9500XL devices incorporate advanced data security fea-
tures which fully protect the programming data against
unauthorized reading or inadvertent device erasure/repro-
gramming.
available.
The read security bits can be set by the user to prevent the
internal programming pattern from being read or copied.
When set, they also inhibit further program operations but
allow device erase. Erasing the entire device is the only way
to reset the read security bit.
The write security bits provide added protection against
accidental device erasure or reprogramming when the
Low Power Mode
All XC9500XL devices offer a low-power mode for individual
macrocells or across all macrocells. This feature allows the
device power to be significantly reduced.
Each individual macrocell may be programmed in
low-power mode by the user. Performance-critical parts of
the application can remain in standard power mode, while
other parts of the application may be programmed for
low-power operation to reduce the overall power dissipation.
Macrocells programmed for low-power mode incur addi-
tional delay (t
register setup time. Product term clock to output and prod-
uct term output enable delays are unaffected by the macro-
cell power-setting. Signals switching at rates less than 50 ns
rise/fall time should be assigned to the macrocells config-
ured in low power mode.
DS054 (v2.5) May 22, 2009
Product Specification
Figure 14: System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable
Table 3
R
LP
) in pin-to-pin combinatorial delay as well as
shows the four different security settings
(a)
www.xilinx.com
JTAG pins are subject to noise, such as during system
power-up. Once set, the write-protection may be deacti-
vated when the device needs to be reprogrammed with a
valid pattern with a specific sequence of JTAG instructions.
Table 3: Data Security Options
Timing Model
The uniformity of the XC9500XL architecture allows a sim-
plified timing model for the entire device. The basic timing
model, shown in
that use the direct product terms only, with standard power
setting, and standard slew rate setting.
each of the key timing parameters is affected by the product
term allocator (if needed), low-power setting, and slew-lim-
ited setting.
The product term allocation time depends on the logic span
of the macrocell function, which is defined as one less than
the maximum number of allocators in the product term path.
If only direct product terms are used, then the logic span is
0. The example in
terms are available with a span of 1. In the case of
the 18 product term function has a span of 2.
XC9500XL High-Performance CPLD Family Data Sheet
Default
Set
Figure
(b)
Program/Erase
Program/Erase
Figure 6
Read Allowed
Read Allowed
Allowed
Allowed
Default
15, is valid for macrocell functions
DS054_14_052209
shows that up to 15 product
Read Security
Program Inhibited
Table 4
Program/Erase
Read Inhibited
Read Inhibited
Erase Allowed
Inhibited
Set
shows how
Figure
14
7,