EPM3064ATC100-10N Altera, EPM3064ATC100-10N Datasheet - Page 13

IC MAX 3000A CPLD 64 100-TQFP

EPM3064ATC100-10N

Manufacturer Part Number
EPM3064ATC100-10N
Description
IC MAX 3000A CPLD 64 100-TQFP
Manufacturer
Altera
Series
MAX® 3000Ar
Datasheet

Specifications of EPM3064ATC100-10N

Programmable Type
In System Programmable
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
4
Number Of Macrocells
64
Number Of Gates
1250
Number Of I /o
66
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Voltage
3.0 V ~ 3.6 V
Memory Type
EEPROM
Number Of Logic Elements/cells
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Other names
544-1974
EPM3064ATC100-10N
In–System
Programma-
bility
Altera Corporation
f
MAX 3000A devices can be programmed in–system via an industry–
standard four–pin IEEE Std. 1149.1-1990 (JTAG) interface. In-system
programmability (ISP) offers quick, efficient iterations during design
development and debugging cycles. The MAX 3000A architecture
internally generates the high programming voltages required to program
its EEPROM cells, allowing in–system programming with only a single
3.3–V power supply. During in–system programming, the I/O pins are
tri–stated and weakly pulled–up to eliminate board conflicts. The pull–up
value is nominally 50 kΩ.
MAX 3000A devices have an enhanced ISP algorithm for faster
programming. These devices also offer an ISP_Done bit that ensures safe
operation when in–system programming is interrupted. This ISP_Done
bit, which is the last bit programmed, prevents all I/O pins from driving
until the bit is programmed.
ISP simplifies the manufacturing flow by allowing devices to be mounted
on a printed circuit board (PCB) with standard pick–and–place equipment
before they are programmed. MAX 3000A devices can be programmed by
downloading the information via in–circuit testers, embedded processors,
the MasterBlaster communications cable, the ByteBlasterMV parallel port
download cable, and the BitBlaster serial download cable. Programming
the devices after they are placed on the board eliminates lead damage on
high–pin–count packages (e.g., QFP packages) due to device handling.
MAX 3000A devices can be reprogrammed after a system has already
shipped to the field. For example, product upgrades can be performed in
the field via software or modem.
The Jam STAPL programming and test language can be used to program
MAX 3000A devices with in–circuit testers, PCs, or embedded processors.
For more information on using the Jam STAPL programming and test
language, see
an Embedded
ICR via an Embedded Processor)
the 8051 and Jam
The ISP circuitry in MAX 3000A devices is compliant with the IEEE Std.
1532 specification. The IEEE Std. 1532 is a standard developed to allow
concurrent ISP between multiple PLD vendors.
Processor),
Application Note 88 (Using the Jam Language for ISP & ICR via
Byte-Code).
MAX 3000A Programmable Logic Device Family Data Sheet
Application Note 122 (Using Jam STAPL for ISP &
and
AN 111 (Embedded Programming Using
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