ADSP-BF527KBCZ-6C2 Analog Devices Inc, ADSP-BF527KBCZ-6C2 Datasheet - Page 17

• Manufacturer Part Number: ADSP-BF527KBCZ-6C2
• Description: IC DSP 16BIT 600MHZ 289CSPBGA
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r
• Type: Fixed Pointr

Specifications of ADSP-BF527KBCZ-6C2

• Package / Case: 289-CSPBGA
• Interface: DMA, Ethernet, I²C, PPI, SPI, SPORT, UART, USB
• Clock Rate: 600MHz
• Non-volatile Memory: ROM (32 kB)
• On-chip Ram: 132kB
• Voltage - I/o: 1.8V, 2.5V, 3.3V
• Voltage - Core: 1.10V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Svhc: No SVHC (18-Jun-2010)
• Cache On Chip L1/l2 Memory: 48KB
• Core Frequency Typ: 600MHz
• Dsp Type: Core
• External Supported Memory: SDRAM, SRAM, FLASH, ROM
• Interface Type: SPI, Parallel, 2 Wire
• Rohs Compliant: Yes
• Mmac: 1200
• No. Of Pins: 289
• Package: 289CSP-BGA
• Maximum Speed: 600 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: ADZS-BF527-MPSKIT - BOARD EVAL MEDIA PLAYER BF527ADZS-BF527-EZLITE - BOARD EVAL ADSP-BF527
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Table 5. Register 1 Right-Channel ADC Input Volume
Table 6. Register 2 Left-Channel DAC Volume
Bit Name
RLINBOTH
RINMUTE
RINVOL
Bit Name
LRHPBOTH
LZCEN
LHPVOL
ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
Bits
B8
B7
B[6:0] Left-channel headphone volume control
Bits
B8
B7
B[5:0]
Description
Left-to-right headphone volume
load control
Left-channel zero cross detect enable
Description
Right-to-left line input ADC
data load control
Right-channel input mute
Right-channel PGA volume control
Rev. A | Page 17 of 36 | March 2010
Settings
0 = disable simultaneous loading of left-channel
headphone volume data to right-channel register (default)
1 = enable simultaneous loading of left-channel
headphone volume data to right-channel register
0 = disable (default)
1 = enable
000 0000 to 010 1111 = mute
011 0000 = –73 dB
…
111 1001 = 0 dB (default)
… 1 dB steps up to
111 1111 = +6 dB
Settings
0 = disable simultaneous loading of right-channel
ADC data to left-channel register (default)
1 = enable simultaneous loading of right-channel
ADC data to left-channel register
0 = disable mute
1 = enable mute on data path to ADC (default)
00 0000 = –34.5 dB
… 1.5 dB step up
01 0111 = 0 dB (default)
… 1.5 dB step up
01 1111 = 12 dB
10 0000 = 13.5 dB
10 0001 = 15 dB
10 0010 = 16.5 dB
10 0011 = 18 dB
10 0100 = 19.5 dB
10 0101 = 21 dB
10 0110 = 22.5 dB
10 0111 = 24 dB
10 1000 = 25.5 dB
10 1001 = 27 dB
10 1010 = 28.5 dB
10 1011 = 30 dB
10 1100 = 31.5 dB
10 1101 = 33 dB
11 1111 to 10 1101 = 33 dB