ADSP-21262SKBCZ200 Analog Devices Inc, ADSP-21262SKBCZ200 Datasheet - Page 35

• Manufacturer Part Number: ADSP-21262SKBCZ200
• Description: IC DSP CTLR 32BIT 136CSPBGA
• Manufacturer: Analog Devices Inc
• Series: SHARC®r
• Type: Fixed/Floating Pointr

Specifications of ADSP-21262SKBCZ200

• Interface: DAI, SPI
• Clock Rate: 200MHz
• Non-volatile Memory: ROM (512 kB)
• On-chip Ram: 256kB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 136-CSPBGA
• No. Of Bits: 32 Bit
• Frequency: 200MHz
• Supply Voltage: 1.2V
• Embedded Interface Type: SPI
• No. Of I/o's: 23
• Supply Voltage Range: 1.14V To 1.26V, 3.13V To 3.47V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADSP21262SKBCZ200

SPI Protocol—Slave
See
Table 30. SPI Protocol—Slave
Parameter
Timing Requirements
t
t
t
t
t
t
t
t
Switching Characteristics
t
t
t
t
t
SPICLKS
SPICHS
SPICLS
SDSCO
HDS
SSPIDS
HSPIDS
SDPPW
DSOE
DSDHI
DDSPIDS
HDSPIDS
DSOV
Table 30
and
Figure
Serial Clock Cycle
Serial Clock High Period
Serial Clock Low Period
SPIDS Assertion to First SPICLK Edge
CPHASE = 0
CPHASE = 1
Last SPICLK Edge to SPIDS Not Asserted CPHASE = 0
Data Input Valid to SPICLK Edge (Data Input Setup Time)
SPICLK Last Sampling Edge to Data Input Not Valid
SPIDS Deassertion Pulse Width (CPHASE = 0)
SPIDS Assertion to Data Out Active
SPIDS Deassertion to Data High Impedance
SPICLK Edge to Data Out Valid (Data Out Delay Time)
SPICLK Edge to Data Out Not Valid (Data Out Hold Time)
SPIDS Assertion to Data Out Valid (CPHASE = 0)
26.
Rev. B | Page 35 of 48 | August 2005
2 × t
Min
4 × t
2 × t
2 × t
2 × t
2 × t
2 × t
2
2
2 × t
0
0
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
– 2
– 2
+ 1
+ 1
– 2
Max
5
5
7.5
5 × t
CCLK
+ 2
ADSP-21262
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns