DSPB56724AG Freescale Semiconductor, DSPB56724AG Datasheet
DSPB56724AG
Specifications of DSPB56724AG
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DSPB56724AG Summary of contents
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... With two DSP56300 cores, a single DSP56724/ DSP56725 device can replace dual-DSP designs, saving costs while This document contains information on a product under development. Freescale reserves the right to change or discontinue this product without notice. © Freescale Semiconductor, Inc., 2009. All rights reserved. Document Number: DSP56724EC DSP56724/DSP56725 DSP56724 144-Pin LQFP 20 mm × ...
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... Pinout for DSP56724 144-Pin Plastic LQFP 4.1.2 Pinout for DSP56725 80-Pin Plastic LQFP Package 4.1.3 Pin Multiplexing . . . . . . . . . . . . . . . . . . . . . . . . Protocol Timing.21 4.2 144-Pin Package Outline Drawing 4.3 80-Pin Package Outline Drawing . . . . . . . . . . . . . . . . . 44 5 Product Documentation Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2 Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 41 Freescale Semiconductor ...
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... On-Chip Memory Shared Bus PCU / AGU DMA OnCE / ALU MODA0, MODB0, MODC0, MODD0 ™ Symphony Freescale Semiconductor EXTAL/XTAL CGM ASRC Arbiter 9 Arbiter 8 Shared Bus 1 Arbiters 0–7 Shared Memory 4 Kbytes Blocks 0–7 (32 Kbytes total) 2 JTAGs JTAG Figure 1. DSP56724 Block Diagram EXTAL/XTAL CGM ...
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... Ratings” Characteristics” Requirements” Characteristics” Characteristics” Clocks” Operation” CAUTION NOTE DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2 See on page 4 on page 6 on page 6 on page 8 on page 9 on page 9 on page 10 Timing” on page Freescale Semiconductor ...
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... Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the maximum rating may affect device reliability or cause permanent damage to the device. ™ Symphony Freescale Semiconductor Table 2. Maximum Ratings 1 DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2 ...
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... Core_VDD Core_VDD IO_VDD DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2 LQFP Values ° 57 for 80 QFP or θ 49 for 144 QFP JA ° 44 for 80 QFP 40 for 144 QFP or θ ° 10 for 80 QFP JC 9 for 144 QFP External Schottky Diode Freescale Semiconductor Unit C/W C/W C/W ...
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... MIPS value. I/MIPS = I/MHz = (I where : I =current at F2 typF2 I =current at F1 typF1 F2=high frequency (any specified operating frequency) F1=low frequency (any specified operating frequency lower than F2) ™ Symphony Freescale Semiconductor must be < × × Example 1. Power Consumption Example – ...
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... CCS DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2 Typ Max Unit V 1.0 1.05 1.2 1.26 3.3 3.45 V — IO_VDD — 0.8 V μA — ± 80 2.057 — pF μA — 10 — — V — 0 142 kΩ 91 159 kΩ 280 60 250 mA 30 220 mA Freescale Semiconductor ...
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... V OL 1.1.7 Internal Clocks Table 5 lists the internal clocks. No. Characteristics 1 Comparison Frequency 2 Input Clock Frequency • with PLL enabled • with PLL disabled ™ Symphony Freescale Semiconductor Symbol Min I — CCI I — CCW I — CCS C — 3 25° C. Maximum internal supply current is measured with ...
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... Etc + Figure 7. External Clock Timing DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2 Max Unit Condition 500 MHz Fvco = (Fin * NF)/NR 200 or 250 MHz Fout = Fvco/NO 200 or 250 Fout = Fin DF 200 or 250 MHz Fsys = Fout/2 200 Fsys = Fout Figure Midpoint Freescale Semiconductor ...
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... Mode select hold time 16 Minimum edge-triggered interrupt request assertion width 17 Minimum edge-triggered interrupt request deassertion width 18 Delay from interrupt trigger to interrupt code execution ™ Symphony Freescale Semiconductor Table 6. Clock Operation Symbol Eth Etl Etc Tc < 1.05 V and –40 < Tj < 100° C VDD_CORE < ...
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... PLL 200 C LOCK 10 × 3.8 — 53 × T — 60 × T — 40 × T — 40 × T — 60 × T — 30 × T — 35 × T — 10 × T — 15 valid, and the EXTAL input is active and DD Freescale Semiconductor Unit μs — — ns μs — μs — ...
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... First Interrupt Instruction Execution IRQA, IRQB, IRQC, IRQD, NMI, NMI_1 b) General Purpose I/O General Purpose I/O IRQA, IRQB, IRQC, IRQD, NMI, NMI_1 ™ Symphony Freescale Semiconductor 11 10 Reset Value Figure 8. Reset Timing Figure 9. External Fast Interrupt Timing DSP56724/ DSP56725 Multi-Core Audio Processors, Rev ...
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... Timing” Timing” Timing” Timing” Specifications—DSP56724” DSP56724/ DSP56725 Multi-Core Audio Processors, Rev IRQA, IRQB, IL IRQC,IRQD, NMI See on page 4 on page 6 on page 6 on page 8 on page 29 on page 30 on page 32 on page 33 on page 34 Freescale Semiconductor ...
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... Minimum serial clock cycle = t SPICC XX Tolerable Spike width on data or clock in. 24 Serial clock high period 25 Serial clock low period 26 Serial clock rise/fall time ™ Symphony Freescale Semiconductor Mode Filter Mode (min) Master/Slave Bypassed Very Narrow Narrow Wide — Bypassed Very Narrow ...
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... — × — × — — 100.0 — ns — 5 — ns — — — — — — 110 ns — — 135 ns — — 225 ns — 10 — ns — 15 — ns — 55 — ns — 105 — ns — — 14.0 ns Freescale Semiconductor ...
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... All times assume noise free inputs. 4. All times assume internal clock frequency of 200 MHz. 5. SHI_1 specs match those of SHI 6. Slave timings should equal the serial clock high period + the serial clock low period. ™ Symphony Freescale Semiconductor Mode Filter Mode Slave Bypassed Very Narrow ...
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... SPI master timing (CPHA = 0). SS (Input) SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) 29 MISO (Input) MOSI (Output) 40 HREQ (Input) ™ Symphony m29 30 MSB Valid 33 MSB 41 42 Figure 12. SPI Master Timing (CPHA = 0) DSP56724/ DSP56725 Multi-Core Audio Processors, Rev LSB Valid 34 LSB Freescale Semiconductor ...
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... Figure 13 shows the SPI master timing (CPHA = 1). SS (Input) SCK (CPOL = 0) (Output) SCK (CPOL = 1) (Output) MISO (Input) MOSI (Output) 40 HREQ (Input) ™ Symphony Freescale Semiconductor MSB Valid 33 MSB 41 42 Figure 13. SPI Master Timing (CPHA = 1) DSP56724/ DSP56725 Multi-Core Audio Processors, Rev LSB ...
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... SPI slave timing (CPHA = 0). SS (Input) SCK (CPOL = 0) (Input) SCK (CPOL = 1) (Input) 31 MISO (Output) 29 MOSI (Input) HREQ (Output) ™ Symphony MSB 30 MSB Valid 36 Figure 14. SPI Slave Timing (CPHA = 0) DSP56724/ DSP56725 Multi-Core Audio Processors, Rev LSB 29 30 LSB Valid 38 Freescale Semiconductor ...
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... XX Tolerable Spike Width on SCL or SDA Filters Bypassed Very Narrow Filters enabled Narrow Filters enabled Wide Filters enabled. 44 SCL clock frequency 44 SCL clock cycle 45 Bus free time 46 Start condition set-up time ™ Symphony Freescale Semiconductor MSB 29 30 MSB Valid Figure 15. SPI Slave Timing (CPHA = 1) ...
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... Freescale Semiconductor Unit μs μs μ μs MHz MHz MHz MHz μs μ ...
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... C mode, the user may select a value for the programmed serial clock cycle from 6 × 4096 × T The programmed serial clock cycle (T shown in next × 45ns + T I CCP C ™ Symphony Freescale Semiconductor 2 C Protocol Timing (Continued) 2 Standard I C Symbol/ Expression T AS;RQI t HO;RQI = bus compliant signal without any issue ...
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... Max Condition 4 × 20.0 — × 20.0 — × — — 2 × — — 2 × — — 2 × — — — — 17 — 7 — — 17 — 7 — — 19 — 9 — — 19 — 9 — — 16 — 6 — — 17 — 7 Freescale Semiconductor 4 Unit ...
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... SCKT rising edge to transmitter #0 drive enable 7 deassertion 89 FST input (bl, wr) setup time before SCKT falling edge 90 FST input (wl) setup time before SCKT falling edge 91 FST input hold time after SCKT falling edge ™ Symphony Freescale Semiconductor Symbol Expression — — 6 — — — — — ...
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... Symbol Expression — — — — — — DSP56724/ DSP56725 Multi-Core Audio Processors, Rev Min Max Condition — — 21.0 — — — 14.0 — — — 14 — 9 × — — C — — 18.0 — — — 18.0 — Freescale Semiconductor 4 Unit ...
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... Drive Enable (Internal Signal) FST (Bit) In FST (Word) In Flags Out Note: In network mode, output flag transitions can occur at the start of each time slot within the frame. In normal mode, the output flag state is asserted for the entire frame period. ™ Symphony Freescale Semiconductor ...
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... FSR (Word) Out Data In FSR (Bit) In FSR (Word) In Flags In Figure 19 shows the ESAI HCKT timing diagram. HCKT SCKT(output) ™ Symphony First Bit Figure 18. ESAI Receiver Timing 95 96 Figure 19. ESAI HCKT Timing DSP56724/ DSP56725 Multi-Core Audio Processors, Rev Last Bit 75 77 Freescale Semiconductor ...
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... Minimum GPIO pulse low width 106 GPIO out rise time 107 GPIO out fall time Note: 1. 0.95 V < V < 1.05 V and Tj < 100° VDD_CORE 2. Simulation numbers-subject to change. ™ Symphony Freescale Semiconductor 95 97 Figure 20. ESAI HCKR Timing Table 12. GPIO Timing 1 Characteristics DSP56724/ DSP56725 Multi-Core Audio Processors, Rev ...
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... DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2 100 101 105 107 All Frequencies Unit Min Max — 10.0 MHz 100.0 — ns 50.0 — ns — 3.0 ns 15.0 — ns 24.0 — ns — 40.0 ns — 40.0 ns 5.0 — ns 25.0 — ns — 44.0 ns — 44.0 ns Freescale Semiconductor ...
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... Figure 23 shows the debugger port timing diagram. TCK VIL (Input) Data Inputs Data Outputs Data Outputs Data Outputs ™ Symphony Freescale Semiconductor 109 110 Figure 22. Test Clock Input Timing Diagram 112 Input Data Valid 114 Output Data Valid 115 114 Output Data Valid Figure 23 ...
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... Delay from timer clear to rise of WDT, WDT_1 ™ Symphony 32 116 Input Data Valid 118 Output Data Valid 119 118 Output Data Valid Table 14. Watchdog Timer Timing DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2 VIH 117 Expression Min Max Unit 2 × 10.0 — × Tc 10.0 — ns Freescale Semiconductor ...
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... STCLK period STCLK high period STCLK low period Figure 25 shows the SRCK timing diagram. SRCK (Output) Figure 26 shows the STCLK timing diagram. STCLK (Input) ™ Symphony Freescale Semiconductor Table 15. S/PDIF Timing Symbol — — — — — — — srckp srckph srckpl ...
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... T — 160 clk_skew T 3 — in_s T 2 — in_h T 12 — gta T 12 — upwait T 3 — ale_h T 3.8 — ale T 4 — out_s T 2 — out_h T 3.5 — ad_s T 1.5 — ad_h T — 4.3 ad_z Freescale Semiconductor Unit ...
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... EMC signals diagram, with EMC PLL enabled. LCLK LSYNC_OUT LSYNC_IN LAD[23:0] (data) LGTA LUPWAIT Output Signals LA[2:0]/LBCTL/LCS[7:0] LOE/LWE LCKE/LSDA10/LSDDQM LSDWE/LSDRAS/LSDCAS LGPL[5:0] LAD[23:0] LALE Figure 27. EMC Signals (EMC PLL Enabled; LCRR[CLKDIV ™ Symphony Freescale Semiconductor T clk_skew T sync_in_skew T asynchronous input T T asynchronous input upwait T T out_s out_h ...
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... Symphony 36 Symbol T clk T in_s 1 T in_h T gta T upwait T ale_h T ale T out_s T out_h T ad_s T ad_h T ad_z DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2 Min Max Unit 4 × — — ns –1 — — — — — — — — — ns — 8.1 ns Freescale Semiconductor ...
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... Input setup to LCLK (except LGTA/LUPWAIT) Input hold from LCLK (except LGTA/LUPWAIT) LGTA valid time LUPWAIT valid time LALE negedge to LAD (address phase) invalid (address latch hold time) LALE valid time ™ Symphony Freescale Semiconductor T in_s asynchronous input T gta T asynchronous input upwait ...
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... T T out_s out_h ad_s ad_h T T ale_h ale DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2 Min Max T 19 — out_s T 18 — out_h T 18 — ad_s T 17 — ad_h T — 17.1 ad_z T clk in_s T in_h gta ad_z Freescale Semiconductor Unit ...
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... Refer to the Symphony™ DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual (DSP56724RM) for detailed functional and applications information. 3 Ordering Information Table 19 shows the ordering information for the DSP56724/DSP56725 devices. Device Device Marking DSP56724 DSPB56724AG DSP56724 DSPB56724CAG DSP56725 DSPB56725AF DSP56725 DSPB56725CAF Contact your local Freescale sales representative for ordering information. 4 Package Information This section provides package and pinout information ...
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... PINIT/NMI 104 TDO 103 TDI 102 TCK 101 TMS 100 SDO2_1/SDI3_1 99 SDO3_1/SDI2_1 98 SDO4_1/SDI1_1 97 SDO5_1/SDI0_1 96 CORE_GND 95 CORE_VDD 94 FSR 93 SCKR 92 HCKR 91 SCKT 90 FST 89 HCKT 88 SDO2/SDI3 87 SDO3/SDI2 86 SDO4/SDI1 85 SDO5/SDI0 84 SPDIFOUT1 83 SPDIFIN1 82 IO_GND 81 IO_VDD 80 EXTAL 79 XTAL 78 PLLP_GND 77 PLLD_GND 76 PLLD_VDD 75 PLLA_GND 74 PLLA_VDD 73 PLLP_VDD Freescale Semiconductor ...
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... Many pins are multiplexed, and depending on the selected configuration, can be one of three possible signals. For more about pin multiplexing, refer to the Symphony™ DSP56724/DSP56725 Multi-Core Audio Processors Reference Manual (DSP56724RM). ™ Symphony Freescale Semiconductor DSP56725 80-Pin Figure 31. DSP56725 80-Pin Package DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2 ...
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... Package Outline Drawing The 144-pin package outline drawing is shown in Figure 32. 144-Pin Package Outline Drawing ™ Symphony 42 Figure 32 and Figure 33. DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2 Freescale Semiconductor ...
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... This dimension does not include dam bar protrusion. Protrusions shall not cause the lead width to exceed 0.35 mm. Minimum space between protrusion and an adjacent lead shall be 0.07 mm. 7 These dimensions are determined at the seating plane, datum A. ™ Symphony Freescale Semiconductor DSP56724/ DSP56725 Multi-Core Audio Processors, Rev ...
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... Package Outline Drawing The 80-pin package outline drawing is shown in ™ Symphony 44 Figure 34 and Figure 35. Figure 34. 80-Pin Package Outline Drawing DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2 Freescale Semiconductor ...
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... Dimensions do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions include mold mismatch and are determined at datum plane H. 7 Dimension does not include dambar protrusion Dambar protrusion shall not cause the lead width to exceed 0.46 mm. Minimum space between protrusion and adjacent lead or protrusion is 0.07mm. ™ Symphony Freescale Semiconductor DSP56724/ DSP56725 Multi-Core Audio Processors, Rev ...
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... LCLK to output high impedance for LAD [23:0],” changed 19 to 17.1 • In Table 19, “Ordering Information,” added rows for DSPB56724CAG and DSPB56725CAF, and changed “DSPA56724AG” to “DSPB56724AG.” • Initial public release. DSP56724/ DSP56725 Multi-Core Audio Processors, Rev. 2 Order Number DSP56300FM ...
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... Symphony Freescale Semiconductor THIS PAGE INTENTIONALLY BLANK DSP56724/ DSP56725 Multi-Core Audio Processors, Rev ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...