KMSC8126VT8000 Freescale Semiconductor, KMSC8126VT8000 Datasheet - Page 18

• Manufacturer Part Number: KMSC8126VT8000
• Description: DSP 16BIT QUAD 500MHZ 431-FCPBGA
• Manufacturer: Freescale Semiconductor
• Series: MSC81xx StarCorer
• Type: SC140 Corer

Specifications of KMSC8126VT8000

• Interface: DSI, Ethernet, RS-232
• Clock Rate: 500MHz
• Non-volatile Memory: External
• On-chip Ram: 1.436MB
• Voltage - I/o: 3.30V
• Voltage - Core: 1.20V
• Operating Temperature: 0°C ~ 90°C
• Mounting Type: Surface Mount
• Package / Case: 431-FCPBGA
• Device Core Size: 16b
• Clock Freq (max): 500MHz
• Mips: 500
• Device Input Clock Speed: 500MHz
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Temp Range: 0C to 90C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 431
• Package Type: FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Electrical Characteristics
In all cases, the power-up sequence must follow the guidelines shown in Figure 8.
The following rules apply:
2.5.3
The following sections include a description of clock signal characteristics. Table 7 shows the maximum frequency values for
internal (Core, Reference, Bus, and DSI) and external (
frequency values are not exceeded.
18
Core frequency
Reference frequency (REFCLK)
Internal bus frequency (BLCK)
DSI clock frequency (HCLKIN)
External clock frequency (CLKIN or CLKOUT)
CLKIN frequency
BCLK frequency
Reference clock (REFCLK) frequency
Output clock (CLKOUT) frequency
SC140 core clock frequency
Note:
1.
2.
3.3 V
1.2 V
During time interval A,
The duration of interval A should be kept below 10 ms.
The duration of timing interval B should be kept as small as possible and less than 10 ms.
V
The rise and fall time of external clocks should be 5 ns maximum
Characteristics
Clock and Timing Signals
Characteristic
Figure 8. Power-Up Sequence for V
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
V
A
DDH
should always be equal to or less than the
Symbol
F
F
F
F
Table 7. Maximum Frequencies
F
CLKOUT
REFCLK
CLKIN
CORE
BCLK
Table 8. Clock Frequencies
B
CLKIN
Min
200
20
40
40
40
and
400 MHz Device
V
CLKOUT
DD
/V
DDH
V
CCSYN
HCLKIN ≤ (min{100 MHz, CLKOUT})
DDH
) clocks. The user must ensure that maximum
and V
133.3
133.3
133.3
133.3
Max
400
(IO)
Maximum in MHz
V
DD
DD
/
V
400/500
133/166
133/166
133/166
/V
CCSYN
CCSYN
voltage level.
Min
200
20
40
40
40
500 MHz Device
Freescale Semiconductor
t (time)
166.7
166.7
166.7
166.7
Max
500