ADSP-2183KST-210 Analog Devices Inc, ADSP-2183KST-210 Datasheet
ADSP-2183KST-210
Specifications of ADSP-2183KST-210
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ADSP-2183KST-210 Summary of contents
Page 1
... ALU operations, I/O memory trans- fers and global interrupt masking, for increased flexibility. Fabricated in a high speed, double metal, low power, CMOS process, the ADSP-2183 operates with instruction cycle time. Every instruction can execute in a single processor cycle. The ADSP-2183’s flexible architecture and comprehensive instruction set allow the processor to perform multiple opera- tions in parallel ...
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... The ADSP-2183 assembly language uses an alge- braic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. Figure overall block diagram of the ADSP-2183. The processor contains three independent computational units: the ALU, the multiplier/accumulator (MAC) and the shifter. The computational units process 16-bit data directly and have provi- sions to support multiprecision computations ...
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... The ADSP-2183 incorporates two complete synchronous serial ports (SPORT0 and SPORT1) for serial communications and multiprocessor communication. Here is a brief list of the capabilities of the ADSP-2183 SPORTs. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for further details. • SPORTs are bidirectional and have a separate, double- buffered transmit and receive section. • ...
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... Ground Pins (Mini-BGA) VDD 11 Power Supply Pins (Mini-BGA) *These ADSP-2183 pins must be connected only to the EZ-ICE connector in the target system. These pins have no function except during emulation, and do not require pull-up or pull-down resistors. Interrupts The interrupt controller allows the processor to respond to the eleven possible interrupts and reset with minimum overhead ...
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... Power-down acknowledge pin indicates when the processor has entered power-down. Idle When the ADSP-2183 is in the Idle Mode, the processor waits indefinitely in a low power state until an interrupt occurs. When an unmasked interrupt occurs serviced; execution then continues with the instruction following the IDLE instruction ...
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... PWDACK IAD15-0 Clock Signals The ADSP-2183 can be clocked by either a crystal or a TTL- compatible clock signal. The CLKIN input cannot be halted, changed during operation or operated below the specified frequency during normal opera- tion. The only exception is while the processor is in the power- down state. For additional information, refer to Chapter 9, ADSP-2100 Family User’ ...
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... The ADSP-2183 contains a 16K × 24 on-chip program RAM. The on-chip program memory is designed to allow up to two accesses each cycle so that all operations can complete in a single cycle. In addition, the ADSP-2183 allows the use of 8K external memory overlays. The program memory space organization is controlled by the MMAP pin and the PMOVLAY register ...
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... BDMA feature. The byte memory space Not Applicable consists of 256 pages, each of which is 16K × LSBs of Address The byte memory space on the ADSP-2183 supports read and Between 0x0000 write operations as well as four different data formats. The byte and 0x1FFF memory uses data bits 15:8 for data ...
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... Internal Memory DMA Port (IDMA Port) The IDMA Port provides an efficient means of communication between a host system and the ADSP-2183. The port is used to access the on-chip program memory and data memory of the DSP with only one DSP cycle per word overhead. The IDMA port cannot, however, be used to write to the DSP’ ...
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... RESET GND The EZ-ICE uses the EE (emulator enable) signal to take con- trol of the ADSP-2183 in the target system. This causes the processor to use its ERESET, EBR and EBG pins instead of the RESET, BR and BG pins. The BG output is three-stated. These signals do not need to be jumper-isolated in your system. ...
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... DSP components statistically vary in switching characteristic and timing require- ments within published limits. Restriction: All memory strobe signals on the ADSP-2183 (RD, WR, PMS, DMS, BMS, CMS and IOMS) used in your target system must have 10 kΩ pull-up resistors connected when the EZ-ICE is being used ...
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... Three-statable pins: A0–A13, D0–D23, PMS, DMS, BMS, IOMS, CMS, RD, WR, DT0, DT1, SCLK0, SCLK1, TFS0, TFS1, RFS0, RFS1, IAD0–IAD15, PF0–PF7 BR, CLKIN Active (to force three-state condition). 19 Idle refers to ADSP-2183 state of operation during execution of IDLE instruction. Deasserted pins are driven to either V 10 Current reflects device operating with no output loads ...
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... ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADSP-2183 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality ...
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... ADSP-2183 Parameter Clock Signals and Reset Timing Requirements: t CLKIN Period CKI t CLKIN Width Low CKIL t CLKIN Width High CKIH Switching Characteristics: t CLKOUT Width Low CKL t CLKOUT Width High CKH t CLKIN High to CLKOUT High CKOH Control Signals Timing Requirement: RESET Width Low ...
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... asynchronous signal meets the setup/hold requirements, it will be recognized during the current clock cycle; otherwise the signal will be recognized on 1 the following cycle. Refer to the ADSP-2100 Family User’s Manual, Third Edition, for BR/BG cycle relationships. 2 BGH is asserted when the bus is granted and the processor requires control of the bus to continue. ...
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... ADSP-2183 Parameter Memory Read Timing Requirements: RD Low to Data Valid t RDD A0–A13, xMS to Data Valid t AA Data Hold from RD High t RDH Switching Characteristics: RD Pulsewidth t RP CLKOUT High to RD Low t CRD A0–A13, xMS Setup before RD Low t ASR A0–A13, xMS Hold after RD Deasserted t RDA ...
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... PMS, DMS, CMS, IOMS, BMS. CLKOUT A0–A13 DMS, PMS, BMS, CMS, IOMS Min 0.5t – 0.25t – 0.5t – 0.25t – 0.25t – 0.25t – 0.75t – 0.25t – 0.5t – WRA WWR ASW CWR WDE ADSP-2183 Max Unit 0. DDR ...
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... ADSP-2183 Parameter Serial Ports Timing Requirements: t SCLK Period SCK t DR/TFS/RFS Setup before SCLK Low SCS t DR/TFS/RFS Hold after SCLK Low SCH t SCLK Width SCP IN Switching Characteristics: t CLKOUT High to SCLK CC t SCLK High to DT Enable SCDE t SCLK High to DT Valid SCDV t TFS/RFS ...
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... Start of Write or Read after Address Latch End IALS NOTES Start of Address Latch = IS Low and IAL High End of Address Latch = IS High or IAL Low. Start of Write or Read = IS Low and IWR Low or IRD Low. 3 IACK IAL IS IAD15–0 IRD OR IWR Min IKA t IALP t t IASU IAH t IALS ADSP-2183 Max Unit ...
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... ADSP-2183 Parameter IDMA Write, Short Write Cycle Timing Requirements: IACK Low before Start of Write t IKW Duration of Write IWP t IAD15–0 Data Setup before End of Write IDSU t IAD15–0 Data Hold after End of Write IDH Switching Characteristic: Start of Write to IACK High t IKHW ...
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... If Write Pulse ends before IACK Low, use specifications Write Pulse ends after IACK Low, use specifications t 4 This is the earliest time for IACK Low from Start of Write. For IDMA Write Cycle relationships, please refer to the ADSP-21xx Family User’s Manual, Third Edition. IACK IS IWR IAD15– ...
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... ADSP-2183 Parameter IDMA Read, Long Read Cycle Timing Requirements: IACK Low before Start of Read t IKR t Duration of Read IRP Switching Characteristics: IACK High after Start of Read t IKHR t IAD15–0 Data Setup before IACK Low IKDS t IAD15–0 Data Hold after End of Read ...
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... IAD15–0 Previous Data Enabled after Start of Read IRDE t IAD15–0 Previous Data Valid after Start of Read IRDV NOTES Start of Read = IS Low and IRD Low End of Read = IS High or IRD High. IAD15–0 Min IACK t IKR t IKHR IS t IRP IRD t IRDE PREVIOUS DATA t IRDV ADSP-2183 Max IKDH t IKDD Unit ...
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... VALID FOR ALL TEMPERATURE GRADES. 1 POWER REFLECTS DEVICE OPERATING WITH NO OUTPUT LOADS. 2 IDLE REFERS TO ADSP-2183 STATE OF OPERATION DURING EXECUTION OF IDLE INSTRUCTION. DEASSERTED PINS ARE DRIVEN TO EITHER V 3 TYPICAL POWER DISSIPATION AT 3. MEASUREMENT TAKEN WITH ALL INSTRUCTIONS EXECUTING FROM INTERNAL DD MEMORY. 50% OF THE INSTRUCTIONS ARE MULTIFUNCTION (TYPES 1,4,5,12,13,14), 30% ARE TYPE 2 AND TYPE 6, AND 20% ARE IDLE INSTRUCTIONS ...
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... CAPACITIVE LOADING Figures 22 and 23 show the capacitive loading characteristics of the ADSP-2183 + 3. 100 120 C – NOMINAL –2 –4 – 120 C – TEST CONDITIONS Output Disable Time Output pins are considered to be disabled when they have stopped driving and started a transition from the measured output high or low voltage to a high impedance state ...
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... A7 XTAL 23 CLKIN 24 GND 25 CLKOUT 26 GND A10 31 32 A11 A12 33 A13 34 IRQE 35 MMAP 36 PWD 37 IRQ2 38 128-Lead LQFP Package Pinout ADSP-2183 TOP VIEW (Not to Scale) 102 GND 101 D23 100 D22 99 D21 98 D20 97 D19 96 D18 95 D17 94 D16 93 D15 92 GND GND 89 D14 88 D13 87 D12 ...
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... D13 RFS1/IRQ0 89 D14 GND 90 GND DR1/FI 91 VDD SCLK1 92 GND ERESET 93 D15 RESET 94 D16 EMS 95 D17 EE 96 D18 ADSP-2183 LQFP Pin Number Name 97 D19 98 D20 99 D21 100 D22 101 D23 102 GND IWR 103 IRD 104 105 IAD15 106 IAD14 107 IAD13 ...
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... ADSP-2183 IWR GND GND IRD D21 D23 D17 D20 D22 GND D15 D18 D14 GND VDD D10 D11 D13 GND D2 GND VDD VDD D1 EBG BR EBR EINT ELOUT ELIN EMS ECLK EE 144-Lead Mini-BGA Package Pinout (Bottom View IAD14 IAD10 IAD6 GND IAD2 ...
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... VDD IRQL1 IAD4 J06 D8 J07 SCLK0 IAD12 J08 RFS1 D12 J09 BG D13 J10 D1 D11 J11 VDD D10 J12 VDD ADSP-2183 Ball # Name K01 A9 K02 A12 K03 A11 K04 PWDACK K05 FL2 K06 TFS0 K07 TFS1 K08 SCLK1 ERESET K09 K10 EBR ...
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... ADSP-2183 128-Lead Metric Plastic Thin Quad Flatpack (LQFP) 0.75 (0.030) 0.60 (0.024) 0.50 (0.020) SEATING 0.08 (0.003) MAX LEAD COPLANARITY 0.15 (0.006) 0.05 (0.002) OUTLINE DIMENSIONS Dimensions given in mm and (inches). (ST-128) 16.20 (0.638) 16.00 (0.630) 1.60 (0.063) 15.80 (0.622) MAX ...
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... ADSP-2183KST-133 0°C to +70°C ADSP-2183BST-133 –40°C to +85°C ADSP-2183KST-160 0°C to +70°C ADSP-2183BST-160 –40°C to +85°C ADSP-2183KST-210 0°C to +70°C ADSP-2183KCA-210 0°C to +70°C OUTLINE DIMENSIONS Dimensions given in mm and (inches). 144-Lead Mini-BGA Package Pinout (CA-144) 0.346 ...