EP1K10TC100-3 Altera, EP1K10TC100-3 Datasheet - Page 12
Manufacturer Part Number
IC ACEX 1K FPGA 10K 100-TQFP
Specifications of EP1K10TC100-3
Number Of Logic Elements/cells
Number Of Labs/clbs
Total Ram Bits
Number Of I /o
Number Of Gates
Voltage - Supply
2.375 V ~ 2.625 V
0°C ~ 70°C
Package / Case
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 5. ACEX 1K EAB Memory Configurations
Figure 6. Examples of Combining ACEX 1K EABs
EABs can be used to implement synchronous RAM, which is easier to use
than asynchronous RAM. A circuit using asynchronous RAM must
generate the RAM write enable signal, while ensuring that its data and
address signals meet setup and hold time specifications relative to the
write enable signal. In contrast, the EAB’s synchronous RAM generates its
own write enable signal and is self-timed with respect to the input or write
clock. A circuit using the EAB’s self-timed RAM must only meet the setup
and hold time specifications of the global clock.
When used as RAM, each EAB can be configured in any of the following
sizes: 256 16; 512 8; 1,024
EAB memory configurations.
Larger blocks of RAM are created by combining multiple EABs. For
example, two 256 16 RAM blocks can be combined to form a 256 32
block, and two 512 8 RAM blocks can be combined to form a
512 16 block.
shows examples of multiple EAB combination.
4; or 2,048 2.
shows the ACEX 1K