EP1K10TC100-3 Altera, EP1K10TC100-3 Datasheet - Page 32

IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3

Manufacturer Part Number
EP1K10TC100-3
Description
IC ACEX 1K FPGA 10K 100-TQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet

Specifications of EP1K10TC100-3

Number Of Logic Elements/cells
576
Number Of Labs/clbs
72
Total Ram Bits
12288
Number Of I /o
66
Number Of Gates
56000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1027
ACEX 1K Programmable Logic Device Family Data Sheet
32
OE0
OE1
OE2
OE3
OE4
OE5
CLKENA0/CLK0/GLOBAL0
CLKENA1/OE6/GLOBAL1
CLKENA2/CLR0
CLKENA3/OE7/GLOBAL2
CLKENA4/CLR1
CLKENA5/CLK1/GLOBAL3
Table 7. Peripheral Bus Sources for ACEX Devices
Peripheral Control Signal
When dedicated inputs drive non-inverted and inverted peripheral clears,
clock enables, and output enables, two signals on the peripheral control
bus will be used.
Table 7
the output enable, clock enable, clock, and clear signals share
12 peripheral control signals.
global signals.
Signals on the peripheral control bus can also drive the four global signals,
referred to as GLOBAL0 through GLOBAL3. An internally generated signal
can drive a global signal, providing the same low-skew, low-delay
characteristics as a signal driven by an input pin. An LE drives the global
signal by driving a row line that drives the peripheral bus which then
drives the global signal. This feature is ideal for internally generated clear
or clock signals with high fan-out. However, internally driven global
signals offer no advantage over the general-purpose interconnect for
routing data signals.
The chip-wide output enable pin is an active-high pin that can be used to
tri-state all pins on the device. This option can be set in the Altera
software. The built-in I/O pin pull-up resistors (which are active during
configuration) are active when the chip-wide output enable pin is
asserted. The registers in the IOE can also be reset by the chip-wide reset
pin.
lists the sources for each peripheral control signal and shows how
EP1K10
Row A
Row A
Row B
Row B
Row C
Row C
Row A
Row A
Row B
Row B
Row C
Row C
EP1K30
Row A
Row B
Row C
Row D
Row E
Row A
Row B
Row C
Row D
Row E
Row F
Row F
Table 7
also shows the rows that can drive
EP1K50
Row D
Row H
Row C
Row G
Row A
Row B
Row F
Row A
Row E
Row J
Row J
Row I
Altera Corporation
EP1K100
Row G
Row A
Row C
Row E
Row K
Row D
Row B
Row H
Row L
Row F
Row J
Row I

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