EP1K10TC100-3 Altera, EP1K10TC100-3 Datasheet - Page 42

IC ACEX 1K FPGA 10K 100-TQFP

EP1K10TC100-3

Manufacturer Part Number
EP1K10TC100-3
Description
IC ACEX 1K FPGA 10K 100-TQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet

Specifications of EP1K10TC100-3

Number Of Logic Elements/cells
576
Number Of Labs/clbs
72
Total Ram Bits
12288
Number Of I /o
66
Number Of Gates
56000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1027
ACEX 1K Programmable Logic Device Family Data Sheet
IEEE Std.
1149.1 (JTAG)
Boundary-Scan
Support
42
SAMPLE/PRELOAD
EXTEST
BYPASS
USERCODE
IDCODE
ICR Instructions
Table 14. ACEX 1K JTAG Instructions
JTAG Instruction
Allows a snapshot of signals at the device pins to be captured and examined during
normal device operation and permits an initial data pattern to be output at the device
pins.
Allows the external circuitry and board-level interconnections to be tested by forcing a
test pattern at the output pins and capturing test results at the input pins.
Places the 1-bit bypass register between the TDI and TDO pins, allowing the BST data
to pass synchronously through a selected device to adjacent devices during normal
operation.
Selects the user electronic signature (USERCODE) register and places it between the
TDI and TDO pins, allowing the USERCODE to be serially shifted out of TDO.
Selects the IDCODE register and places it between TDI and TDO, allowing the IDCODE
to be serially shifted out of TDO.
These instructions are used when configuring an ACEX 1K device via JTAG ports using
a MasterBlaster, ByteBlasterMV, or BitBlaster download cable, or a Jam File (.jam) or
Jam Byte-Code File (.jbc) via an embedded processor.
All ACEX 1K devices provide JTAG BST circuitry that complies with the
IEEE Std. 1149.1-1990 specification. ACEX 1K devices can also be
configured using the JTAG pins through the ByteBlasterMV or BitBlaster
download cable, or via hardware that uses the Jam
Programming Language (STAPL), JEDEC standard JESD-71. JTAG
boundary-scan testing can be performed before or after configuration, but
not during configuration. ACEX 1K devices support the JTAG
instructions shown in
The instruction register length of ACEX 1K devices is 10 bits. The
USERCODE register length in ACEX 1K devices is 32 bits; 7 bits are
determined by the user, and 25 bits are pre-determined.
show the boundary-scan register length and device IDCODE information
for ACEX 1K devices.
Table 15. ACEX 1K Boundary-Scan Register Length
EP1K10
EP1K30
EP1K50
EP1K100
Device
Table
14.
Description
Boundary-Scan Register Length
1,050
TM
438
690
798
Standard Test and
Altera Corporation
Tables 15
and
16

Related parts for EP1K10TC100-3