EP1K10QC208-3 Altera, EP1K10QC208-3 Datasheet - Page 15

IC ACEX 1K FPGA 10K 208-PQFP

EP1K10QC208-3

Manufacturer Part Number
EP1K10QC208-3
Description
IC ACEX 1K FPGA 10K 208-PQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet

Specifications of EP1K10QC208-3

Number Of Logic Elements/cells
576
Number Of Labs/clbs
72
Total Ram Bits
12288
Number Of I /o
120
Number Of Gates
56000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
208-MQFP, 208-PQFP
No. Of I/o's
120
Operating Temperature Range
0°C To +70°C
Logic Case Style
QFP
No. Of Pins
208
Peak Reflow Compatible (260 C)
No
No. Of Macrocells
576
Rohs Compliant
No
Clock Management
PLL
Leaded Process Compatible
No
No. Of Gates
10000
No. Of Logic Blocks
72
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1090

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ACEX 1K Programmable Logic Device Family Data Sheet
Each LAB provides four control signals with programmable inversion
that can be used in all eight LEs. Two of these signals can be used as clocks,
the other two can be used for clear/preset control. The LAB clocks can be
driven by the dedicated clock input pins, global signals, I/O signals, or
internal signals via the LAB local interconnect. The LAB preset and clear
control signals can be driven by the global signals, I/O signals, or internal
signals via the LAB local interconnect. The global control signals are
typically used for global clock, clear, or preset signals because they
provide asynchronous control with very low skew across the device. If
logic is required on a control signal, it can be generated in one or more LEs
in any LAB and driven into the local interconnect of the target LAB. In
addition, the global control signals can be generated from LE outputs.
Logic Element
The LE, the smallest unit of logic in the ACEX 1K architecture, has a
compact size that provides efficient logic utilization. Each LE contains a
4-input LUT, which is a function generator that can quickly compute any
function of four variables. In addition, each LE contains a programmable
13
flipflop with a synchronous clock enable, a carry chain, and a cascade
chain. Each LE drives both the local and the FastTrack Interconnect
routing structure.
Figure 8
shows the ACEX 1K LE.
Altera Corporation
15

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