EP1K10QC208-3 Altera, EP1K10QC208-3 Datasheet - Page 24

IC ACEX 1K FPGA 10K 208-PQFP

EP1K10QC208-3

Manufacturer Part Number
EP1K10QC208-3
Description
IC ACEX 1K FPGA 10K 208-PQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet

Specifications of EP1K10QC208-3

Number Of Logic Elements/cells
576
Number Of Labs/clbs
72
Total Ram Bits
12288
Number Of I /o
120
Number Of Gates
56000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
208-MQFP, 208-PQFP
No. Of I/o's
120
Operating Temperature Range
0°C To +70°C
Logic Case Style
QFP
No. Of Pins
208
Peak Reflow Compatible (260 C)
No
No. Of Macrocells
576
Rohs Compliant
No
Clock Management
PLL
Leaded Process Compatible
No
No. Of Gates
10000
No. Of Logic Blocks
72
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1090

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1K10QC208-3
Manufacturer:
ALTERA
Quantity:
509
Part Number:
EP1K10QC208-3
Manufacturer:
ALTERA
Quantity:
996
Part Number:
EP1K10QC208-3
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1K10QC208-3
Manufacturer:
ALTERA
0
Part Number:
EP1K10QC208-3
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP1K10QC208-3N
Manufacturer:
ALTERA20
Quantity:
288
Part Number:
EP1K10QC208-3N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1K10QC208-3N
Manufacturer:
ALTERA
0
ACEX 1K Programmable Logic Device Family Data Sheet
Figure 12. ACEX 1K LE Clear & Preset Modes
24
Asynchronous Load with Clear
Asynchronous Load with Preset
Asynchronous Clear
Chip-Wide Reset
Chip-Wide Reset
(Asynchronous
(Asynchronous
labctrl1 or
(Preset)
labctrl2
labctrl2
labctrl1
labctrl2
(Clear)
labctrl1
(Data)
(Data)
Load)
data3
data3
Load)
NOT
NOT
D
CLRN
VCC
PRN
NOT
NOT
In addition to the six clear and preset modes, ACEX 1K devices provide a
chip-wide reset pin that can reset all registers in the device. Use of this
feature is set during design entry. In any of the clear and preset modes, the
chip-wide reset overrides all other signals. Registers with asynchronous
presets may be preset when the chip-wide reset is asserted. Inversion can
be used to implement the asynchronous preset.
of how to setup the preset and clear inputs for the desired functionality.
Q
Chip-Wide Reset
Chip-Wide Reset
Asynchronous Preset
labctrl1 or
labctrl2
D
CLRN
PRN
VCC
Q
D
CLRN
(Asynchronous
D
PRN
Asynchronous Load without Clear or Preset
CLRN
PRN
Q
Q
labctrl1
(Data)
Load)
data3
Chip-Wide Reset
Asynchronous Preset & Clear
Chip-Wide Reset
NOT
NOT
labctrl2
labctrl1
Figure 12
Altera Corporation
D
shows examples
CLRN
PRN
Q
D
CLRN
PRN
Q

Related parts for EP1K10QC208-3