EP1K10QC208-3 Altera, EP1K10QC208-3 Datasheet - Page 83

• Manufacturer Part Number: EP1K10QC208-3
• Description: IC ACEX 1K FPGA 10K 208-PQFP
• Manufacturer: Altera
• Series: ACEX-1K®r

Specifications of EP1K10QC208-3

• Number Of Logic Elements/cells: 576
• Number Of Labs/clbs: 72
• Total Ram Bits: 12288
• Number Of I /o: 120
• Number Of Gates: 56000
• Voltage - Supply: 2.375 V ~ 2.625 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 208-MQFP, 208-PQFP
• No. Of I/o's: 120
• Operating Temperature Range: 0°C To +70°C
• Logic Case Style: QFP
• No. Of Pins: 208
• Peak Reflow Compatible (260 C): No
• No. Of Macrocells: 576
• Rohs Compliant: No
• Clock Management: PLL
• Leaded Process Compatible: No
• No. Of Gates: 10000
• No. Of Logic Blocks: 72
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 544-1090

Altera Corporation
Figure 31. ACEX 1K I
Configuration &
Operation
EP1K30
I
Current (mA)
CC
Supply
100
80
60
40
20
0
CCACTIVE
The ACEX 1K architecture supports several configuration schemes. This
section summarizes the device operating modes and available device
configuration schemes.
Operating Modes
The ACEX 1K architecture uses SRAM configuration elements that
require configuration data to be loaded every time the circuit powers up.
The process of physically loading the SRAM data into the device is called
configuration. Before configuration, as V
Power-On Reset (POR). This POR event clears the device and prepares it
for configuration. The ACEX 1K POR time does not exceed 50 s.
1
vs. Operating Frequency
EP1K100
I
Current (mA)
Frequency (MHz)
CC
Supply
50
When configuring with a configuration device, refer to the
relevant configuration device data sheet for POR timing
information.
300
200
100
0
100
ACEX 1K Programmable Logic Device Family Data Sheet
Frequency (MHz)
EP1K50
I
Current (mA)
CC
Supply
50
200
150
100
50
CC
0
100
rises, the device initiates a
Frequency (MHz)
50
100
83
13