EP1C3T144C7N Altera, EP1C3T144C7N Datasheet - Page 82

IC CYCLONE FPGA 2910 LE 144-TQFP

EP1C3T144C7N

Manufacturer Part Number
EP1C3T144C7N
Description
IC CYCLONE FPGA 2910 LE 144-TQFP
Manufacturer
Altera
Series
Cyclone®r
Datasheet

Specifications of EP1C3T144C7N

Number Of Logic Elements/cells
2910
Number Of Labs/clbs
291
Total Ram Bits
59904
Number Of I /o
104
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1661

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Cyclone Device Handbook, Volume 1
4–12
Preliminary
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SU
H
CO
PIN2COMBOUT_R
PIN2COMBOUT_C
COMBIN2PIN_R
COMBIN2PIN_C
CLR
PRE
CLKHL
M4KRC
M4KWC
M4KWERESU
M4KWEREH
M4KBESU
M4KBEH
M4KDATAASU
M4KDATAAH
M4KADDRASU
M4KADDRAH
M4KDATABSU
M4KDATABH
M4KADDRBSU
M4KADDRBH
M4KDATACO1
M4KDATACO2
M4KCLKHL
M4KCLR
Table 4–22. IOE Internal Timing Microparameter Descriptions
Table 4–23. M4K Block Internal Timing Microparameter Descriptions
Symbol
Symbol
Synchronous read cycle time
Synchronous write cycle time
Write or read enable setup time before clock
Write or read enable hold time after clock
Byte enable setup time before clock
Byte enable hold time after clock
A port data setup time before clock
A port data hold time after clock
A port address setup time before clock
A port address hold time after clock
B port data setup time before clock
B port data hold time after clock
B port address setup time before clock
B port address hold time after clock
Clock-to-output delay when using output registers
Clock-to-output delay without output registers
Minimum clock high or low time
Minimum clear pulse width
IOE input and output register setup time before clock
IOE input and output register hold time after clock
IOE input and output register clock-to-output delay
Row input pin to IOE combinatorial output
Column input pin to IOE combinatorial output
Row IOE data input to combinatorial output pin
Column IOE data input to combinatorial output pin
Minimum clear pulse width
Minimum preset pulse width
Minimum clock high or low time
Parameter
Parameter
Altera Corporation
May 2008

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