EP2C5F256C8N Altera, EP2C5F256C8N Datasheet - Page 146

IC CYCLONE II FPGA 5K 256-FBGA

EP2C5F256C8N

Manufacturer Part Number
EP2C5F256C8N
Description
IC CYCLONE II FPGA 5K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet

Specifications of EP2C5F256C8N

Number Of Logic Elements/cells
4608
Number Of Labs/clbs
288
Total Ram Bits
119808
Number Of I /o
158
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
No. Of Logic Blocks
288
Family Type
Cyclone II
No. Of I/o's
158
I/o Supply Voltage
3.3V
Operating Frequency Max
320MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1656

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Timing Specifications
Figure 5–3. High-Speed I/O Timing Diagram
5–56
Cyclone II Device Handbook, Volume 1
Sampling window
Receiver input skew
margin
Input jitter (peak to peak)
Output jitter (peak to peak)
Signal rise time
Signal fall time
Lock time
Table 5–47. High-Speed I/O Timing Definitions (Part 2 of 2)
Parameter
Internal Clock
Input Clock
Input Data
Receiver
External
SW
RSKM
t
t
t
R I S E
FA L L
L O C K
Symbol
Figure 5–4
TCCS
The period of time during which the data must be valid in order for you
to capture it correctly. Sampling window is the sum of the setup time,
hold time, and jitter. The window of t
in the sampling window.
SW = TUI – TCCS – (2 × RSKM)
RSKM is defined by the total margin left after accounting for the
sampling window and TCCS.
RSKM = (TUI – SW – TCCS) / 2
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Low-to-high transmission time.
High-to-low transmission time.
Lock time for high-speed transmitter and receiver PLLs.
RSKM
shows the high-speed I/O timing budget.
Sampling Window (SW)
Time Unit Interval (TUI)
Description
SU
RSKM
+ t
H
is expected to be centered
TCCS
Altera Corporation
February 2008

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