EP2C5F256C8N Altera, EP2C5F256C8N Datasheet - Page 148

IC CYCLONE II FPGA 5K 256-FBGA

EP2C5F256C8N

Manufacturer Part Number
EP2C5F256C8N
Description
IC CYCLONE II FPGA 5K 256-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet

Specifications of EP2C5F256C8N

Number Of Logic Elements/cells
4608
Number Of Labs/clbs
288
Total Ram Bits
119808
Number Of I /o
158
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
No. Of Logic Blocks
288
Family Type
Cyclone II
No. Of I/o's
158
I/o Supply Voltage
3.3V
Operating Frequency Max
320MHz
Operating Temperature Range
0°C To +85°C
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1656

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2C5F256C8N
Manufacturer:
ALTBRA
Quantity:
36
Part Number:
EP2C5F256C8N
Manufacturer:
ALTERA82
Quantity:
1 080
Part Number:
EP2C5F256C8N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2C5F256C8N
Manufacturer:
ALTERA/PBF
Quantity:
5
Part Number:
EP2C5F256C8N
Manufacturer:
ALTERA
0
Part Number:
EP2C5F256C8N
Manufacturer:
ALTERA
Quantity:
21
Part Number:
EP2C5F256C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP2C5F256C8N
0
Part Number:
EP2C5F256C8N#####
Manufacturer:
ALTERA
0
Timing Specifications
5–58
Cyclone II Device Handbook, Volume 1
Note to
(1)
TCCS
Output
jitter (peak
to peak)
t
t
t
R I S E
F A L L
L O C K
Table 5–48. RSDS Transmitter Timing Specification (Part 2 of 2)
Symbol
These specifications are for a three-resistor RSDS implementation. For single-resistor RSDS in ×10 through ×2
modes, the maximum data rate is 170 Mbps and the corresponding maximum input clock frequency is 85 MHz.
For single-resistor RSDS in ×1 mode, the maximum data rate is 170 Mbps, and the maximum input clock frequency
is 170 MHz. For more information about the different RSDS implementations, refer to the
Interfaces in Cyclone II Devices
Table
20–80%,
C
80–20%,
C
5–48:
L O A D
L O A D
Conditions
= 5 pF
= 5 pF
In order to determine the transmitter timing requirements, RSDS receiver
timing requirements on the other end of the link must be taken into
consideration. RSDS receiver timing parameters are typically defined as
t
specifications are t
for the timing budget.
The AC timing requirements for RSDS are shown in
Min
SU
–6 Speed Grade
chapter of the Cyclone II Device Handbook.
and t
Typ
500
500
H
requirements. Therefore, the transmitter timing parameter
Max(1)
200
500
100
CO
(minimum) and t
Min
–7 Speed Grade
Typ
500
500
Max(1)
500
100
200
CO
(maximum). Refer to
Min
–8 Speed Grade
Typ
500
500
High-Speed Differential
Figure
Altera Corporation
Max(1)
February 2008
500
100
200
5–5.
Figure 5–4
Unit
ps
ps
ps
ps
μs

Related parts for EP2C5F256C8N