EP3C5F256C8N Altera, EP3C5F256C8N Datasheet

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... Innovation Drive San Jose, CA 95134 www.altera.com CIII5V1-3.3 Cyclone III Device Handbook, Volume 1 ® ...

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... Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera as- sumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation ...

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... About–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . About–1 Chapter 1. Cyclone III Device Family Overview Cyclone III Device Family Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1– ...

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... Cyclone III Device Family PLL Hardware Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10 External Clock Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–10 Clock Feedback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12 Source-Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–12 No Compensation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–13 Zero Delay Buffer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–14 Cyclone III Device Handbook, Volume 1 Contents © January 2010 Altera Corporation ...

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... Voltage-Referenced I/O Standard Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–13 Differential I/O Standard Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–14 I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–16 High-Speed Differential Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20 External Memory Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–20 Pad Placement and DC Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21 Pad Placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21 DC Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6–21 © January 2010 Altera Corporation v Cyclone III Device Handbook, Volume 1 ...

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... Configuration Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8 Power 9–8 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–8 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–9 Configuration Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–9 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–9 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10 Configuration Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10 AS Configuration (Serial Configuration Devices 9–12 Single-Device AS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–12 Multi-Device AS Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–14 Cyclone III Device Handbook, Volume 1 Contents © January 2010 Altera Corporation ...

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... Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–79 Remote Update Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–79 Dedicated Remote System Upgrade Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–82 Remote System Upgrade Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–83 Remote System Upgrade State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–86 User Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–87 Quartus II Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–88 © January 2010 Altera Corporation vii Cyclone III Device Handbook, Volume 1 ...

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... IEEE Std. 1149.1 BST Operation Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2 I/O Voltage Support in a JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–5 Guidelines for IEEE Std. 1149.1 BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–6 Boundary-Scan Description Language Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–7 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–7 Cyclone III Device Handbook, Volume 1 Contents © January 2010 Altera Corporation ...

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... Chapter 9 Configuration, Design Security, and Remote System Upgrades in the Cyclone III De- vice Family Revised: Part Number: CIII51016-1.2 Chapter 10 Hot-Socketing and Power-On Reset in the Cyclone III Device Family Revised: Part Number: CIII51011-3.2 © January 2010 Altera Corporation December 2009 December 2009 December 2009 December 2009 December 2009 December 2009 ...

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... Chapter 11 SEU Mitigation in the Cyclone III Device Family Revised: Part Number: CIII51013-2.2 Chapter 12 IEEE 1149.1 (JTAG) Boundary-Scan Testing for the Cyclone III Device Family Revised: Part Number: CIII51014-2.2 Cyclone III Device Handbook, Volume 1 December 2009 December 2009 Chapter Revision Dates © January 2010 Altera Corporation ...

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... Product literature Altera literature services Non-technical support (General) (Software Licensing) Note to table: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions This document uses the typographic conventions shown below. Visual Cue Bold Type with Initial Capital Letters ...

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... The warning indicates information that should be read prior to starting or continuing the procedure or processes. The angled arrow indicates you should press the Enter key. The feet direct you to more information on a particular topic. Chapter : Typographic Conventions . ), as well as logic © January 2010 Altera Corporation ...

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... Refer to each chapter for its own specific revision history. For information about when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook. © December 2009 Altera Corporation Section 1. Device Core Cyclone III Device Handbook, Volume 1 ® ...

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...

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... Extended battery life for portable and handheld applications ■ Reduced or eliminated cooling system costs ■ Operation in thermally-challenged environments ■ ■ Hot-socketing operation support © December 2009 Altera Corporation 1. Cyclone III Device Family Overview power-aware design flow Cyclone III Device Handbook, Volume 1 ...

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... Nios II embedded processor for Cyclone III device family, offering low cost and ® custom-fit embedded processing solutions Cyclone III Device Handbook, Volume 1 Chapter 1: Cyclone III Device Family Overview Cyclone III Device Family Features II ® © December 2009 Altera Corporation ...

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... Chapter 1: Cyclone III Device Family Overview Cyclone III Device Family Features ■ Wide collection of pre-built and verified IP cores from Altera and Altera Megafunction Partners Program (AMPP) partners ■ Supports high-speed external memory interfaces such as DDR, DDR2, SDR SDRAM, and QDRII SRAM Auto-calibrating PHY feature eases the timing closure process and eliminates ■ ...

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... Altera Device Package Information Data Sheet. Cyclone III Device Family Features (Note 1), (2), (3), (4), (5) F484 U484 F780 — — — — — — 346, 140 346, 140 — ...

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... Cyclone III EP3C40 — EP3C55 — EP3C80 — EP3C120 — EP3CLS70 — EP3CLS100 — Cyclone III LS EP3CLS150 — EP3CLS200 — © December 2009 Altera Corporation 2 Pitch (mm) Nominal Area (mm ) 0.5 484 0.5 64 0.5 1197 1.0 289 0.8 196 1.0 361 1.0 529 0.8 361 1 ...

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... Cyclone III Device Handbook, Volume 1 Configuration Scheme Active serial (AS) Active parallel (AP) Passive serial (PS) Fast passive parallel (FPP) chapter. Chapter 1: Cyclone III Device Family Overview Cyclone III Device Family Architecture Cyclone III Cyclone III — Logic Elements and Logic Array © December 2009 Altera Corporation ...

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... For more PLL specifications and information, refer to the Cyclone III LS Device Data chapters. © December 2009 Altera Corporation Embedded Multipliers in Cyclone III Devices Sheet, and Clock Networks and PLLs in Cyclone III Devices 1–7 Memory Blocks in Cyclone III chapter ...

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... I/O Standard LVTTL, LVCMOS, SSTL, HSTL, PCI, and PCI-X SSTL, HSTL, LVPECL, BLVDS, LVDS, mini-LVDS, RSDS, and PPDS Cyclone III Device I/O Features High-Speed Differential Interfaces in Cyclone III Devices External Memory Interfaces in Cyclone III Devices © December 2009 Altera Corporation OCT chapter. ...

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... Freescale Cortex M1, or Altera Nios the system-on-a-programmable-chip (SOPC) Builder tool. SOPC Builder is an Altera Quartus II design tool that facilitates system-integration of IP blocks in an FPGA design. The SOPC Builder automatically generates interconnect logic and creates a testbench to verify functionality, saving valuable design time ...

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... Cyclone III device family uses SRAM cells to store configuration data. Configuration data is downloaded to Cyclone III device family each time the device powers up. Low-cost configuration options include the Altera EPCS family serial flash devices as well as commodity parallel flash configuration options. These options provide the flexibility for general-purpose applications and the ability to meet specific configuration and wake-up time requirements of the applications ...

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... The configuration security of Cyclone III LS devices uses AES with 256-bit security key. f For more information, refer to the Upgrades in Cyclone III Devices © December 2009 Altera Corporation Configuration, Design Security, and Remote System chapter. Configuration, Design Security, and Remote System chapter. Cyclone III Device Handbook, Volume 1 ...

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... C) J ° ° 100 C) J ° ° 125 C) J Optional Suffix Indicates specific device options or shipment method. ES: Engineering sample N: Lead-free devices Speed Grade 7 (fastest) 8 Operating Temperature ° ° C: Commercial temperature ( ° ° I: Industrial temperature ( 100 C) J © December 2009 Altera Corporation ...

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... May 2008 1.2 July 2007 1.1 March 2007 1.0 © December 2009 Altera Corporation Changes Made Minor text edits. Minor edit to the hyperlinks. Added Table 1–5. ■ Updated Table 1–1, Table 1–2, Table 1–3, and Table 1–4. ■ Updated “Introduction”, “Cyclone III Device Family Architecture”, “Embedded ■ ...

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... Cyclone III Device Handbook, Volume 1 Chapter 1: Cyclone III Device Family Overview Chapter Revision History © December 2009 Altera Corporation ...

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... Column ■ Register chain ■ Direct link ■ ■ Register packing support ■ Register feedback support © December 2009 Altera Corporation 2. Logic Elements and Logic Array Blocks in the Cyclone III Device Family III device family ® Cyclone III Device Handbook, Volume 1 ...

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... Clear Logic Reset (DEV_CLRn) Clock & Clock Enable Select labclk1 LE Carry-Out labclk2 labclkena1 labclkena2 2–6. Logic Elements Row, Column, And Direct Link D Q Routing ENA CLRN Row, Column, And Direct Link Routing Local Routing Register Chain Output © December 2009 Altera Corporation ...

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... Figure 2–2 shows LEs in normal mode. Figure 2–2. Cyclone III Device Family LEs in Normal Mode © December 2009 Altera Corporation II software automatically chooses the appropriate mode for common (Figure 2–2). The Quartus II Compiler automatically selects the Register Chain ...

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... ENA LUT clock (LAB Wide) ena (LAB Wide) aclr (LAB Wide) cout Register Bypass Register Feedback LE Operating Modes Row, Column, and Q Direct link routing D Row, Column, and Direct link routing CLRN Local Routing Register Chain Output © December 2009 Altera Corporation ...

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... LAB structure for the Cyclone III device family. Figure 2–4. Cyclone III Device Family LAB Structure Direct link interconnect from adjacent block Direct link interconnect to adjacent block © December 2009 Altera Corporation Row Interconnect LAB Local Interconnect 2–5 Column Interconnect Direct link interconnect from adjacent block ...

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... Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family PLL, or IOE output Direct link interconnect to left Local Interconnect LAB Control Signals Direct link interconnect from right LAB, M9K memory block, embedded multiplier, PLL, or IOE output Direct link interconnect to right LAB © December 2009 Altera Corporation ...

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... In addition to the clear port, the Cyclone III device family provides a chip-wide reset pin (DEV_CLRn) that resets all registers in the device. An option set before compilation in the Quartus II software controls this pin. This chip-wide reset overrides all other control signals. © December 2009 Altera Corporation 6 labclkena2 labclkena1 labclk1 ...

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... Updated Figure 2–1 on page 2–2 and Figure 2–4 on page 2–5. ■ Updated “LAB Control Signals” on page 2–6. ■ Updated chapter to new template. Removed trademark symbol from “MultiTrack” in “LAB Control Signals” section. Initial release. Chapter Revision History © December 2009 Altera Corporation ...

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... CIII51004-2.2 The Cyclone ® embedded memory structures to address the on-chip memory needs of Altera Cyclone III device family designs. The embedded memory structure consists of columns of M9K memory blocks that you can configure to provide various memory functions, such as RAM, shift registers, ROM, and FIFO buffers. ...

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... Outputs set to Old Data or Don’t Care Cyclone III Device Family Overview Overview M9K Blocks 8192 × 1 4096 × 2 2048 × 4 1024 × 8 1024 × 9 512 × 16 512 × 18 256 × 32 256 × Outputs cleared Output latches only chapter. © December 2009 Altera Corporation ...

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... The Cyclone III device family M9K memory blocks support a parity bit for each storage byte. You can use this bit as either a parity bit additional data bit. No parity function is actually performed on this bit. © December 2009 Altera Corporation clock_b clocken_b rden_b ...

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... Chapter 3: Memory Blocks in the Cyclone III Device Family Affected Bytes datain × 16 datain × 18 [7..0] [8..0] [15..8] [17..9] — — — — Overview (Note 1) datain × 32 datain × 36 [7..0] [8..0] [15..8] [17..9] [23..16] [26..18] [31..24] [35..27] © December 2009 Altera Corporation ...

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... Cyclone III device family M9K memory blocks support an active-low address clock enable, which holds the previous address value for as long as the addressstall signal is high (addressstall = '1'). When you configure M9K memory blocks in dual-port mode, each port has its own independent address clock enable. © December 2009 Altera Corporation ...

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... Figure 3–5 show the address clock enable waveform during read and doutn-1 doutn dout0 dout1 dout0 doutn dout1 dout1 Overview address[0] address[ dout1 dout4 dout1 dout1 dout4 dout5 © December 2009 Altera Corporation ...

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... Asserting asynchronous clear to the read address register during a read operation might corrupt the memory content. Figure 3–6 shows the functional waveform for the asynchronous clear feature. Figure 3–6. Output Latch Asynchronous Clear Waveform clk aclr aclr at latch q © December 2009 Altera Corporation data ...

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... Plug-In Manager. ™ RAM Megafunction User shows the single-port memory configuration for Cyclone III (Note 1), (2) data[ ] address[ ] wren byteena[] addressstall inclock outclock inclocken outclocken rden aclr “Packed Mode Support” on page 3–5. Memory Modes Guide. q[] © December 2009 Altera Corporation ...

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... Registering the outputs of the RAM simply delays the q output by one clock cycle. Figure 3–8. Cyclone III Device Family Single-Port Mode Timing Waveforms clk_a wren_a rden_a address_a data_a q_a (old data) q_a (new data) © December 2009 Altera Corporation 3–16 a0(old data a1(old data) ...

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... Operations” on page Memory Modes (Note 1) rden q[ ] rdclock rdclocken 1024 × 9 512 × 18 256 × 36 — — — — — — — — — — — — — — — — — — 3–16. © December 2009 Altera Corporation ...

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... Figure 3–11. Cyclone III Device Family True Dual-Port Memory Note to Figure 3–11: (1) True dual-port memory supports input or output clock mode in addition to the independent clock mode shown. 1 The widest bit configuration of the M9K blocks in true dual-port mode is 512 × 16-bit (18-bit with parity). © December 2009 Altera Corporation dout0 doutn ...

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... Operations” on page Memory Modes × 8 512 × 16 1024 × 9 512 × — — — — — — — — — — — — — — 3–16. © December 2009 Altera Corporation ...

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... In addition, the size of (w × n) must be less than or equal to the maximum width of the block, which is 36 bits. If you need a larger shift register, you can cascade the M9K memory blocks. © December 2009 Altera Corporation ...

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... FIFO buffer. f For more information about FIFO buffers, refer to the Megafunction User Cyclone III Device Handbook, Volume 1 Chapter 3: Memory Blocks in the Cyclone III Device Family Guide. Memory Modes Number of Taps W W Single- and Dual-Clock FIFO © December 2009 Altera Corporation ...

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... An output clock controls the data-output registers. Each memory block port also supports independent clock enables for input and output registers. © December 2009 Altera Corporation Simple True Dual-Port Single-Port Dual-Port ...

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... Cyclone III Device Handbook, Volume 1 Chapter 3: Memory Blocks in the Cyclone III Device Family and “Mixed-Port Read-During- describe the functionality of the various RAM write_b Port B data in Port B read_b data out © December 2009 Altera Corporation Design Considerations Figure 3–14 Mixed-port data flow Same-port data flow ...

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... Figure 3–15. Same Port Read-During Write: New Data Mode clk_a wren_a rden_a address_a data_a q_a (asynch) Figure 3–16. Same Port Read-During-Write: Old Data Mode clk_a wren_a rden_a address_a data_a q_a (asynch) © December 2009 Altera Corporation Figure 3–16 show sample functional waveforms of same port ...

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... Therefore, you must implement conflict-resolution logic external to the M9K memory block. Cyclone III Device Handbook, Volume 1 Chapter 3: Memory Blocks in the Cyclone III Device Family Guide (old data (old data) Design Considerations RAM © December 2009 Altera Corporation ...

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... May 2008 1.2 July 2007 1.1 March 2007 1.0 © December 2009 Altera Corporation RAM Megafunction User Guide Changes Made Minor changes to the text. Made minor correction to the part number. Updated to include Cyclone III LS information Updated chapter part number. ■ ...

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... Cyclone III Device Handbook, Volume 1 Chapter 3: Memory Blocks in the Cyclone III Device Family Chapter Revision History © December 2009 Altera Corporation ...

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... Figure 4–1. Embedded Multipliers Arranged in Columns with Adjacent LABs © December 2009 Altera Corporation 4. Embedded Multipliers in the Cyclone III Device Family III device family (Cyclone III and Cyclone III LS devices) includes a ...

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... Embedded Multipliers (16 × 16) 23 — 126 126 156 260 244 305 288 432 Embedded Multiplier Block Overview × 18 Multipliers ( 126 156 244 288 200 276 320 396 Total Multipliers (2) ( 112 132 252 416 549 720 © December 2009 Altera Corporation ...

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... Multiplier stage Input and output registers ■ Input and output interfaces ■ Figure 4–2 shows the multiplier block architecture. Figure 4–2. Multiplier Block Architecture Data A Data B © December 2009 Altera Corporation Soft Multipliers Embedded Multipliers (16 × 16) 200 333 276 483 320 666 ...

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... Cyclone III Device Handbook, Volume 1 Chapter 4: Embedded Multipliers in the Cyclone III Device Family 4–5. Data A Logic Level signb Value Low Unsigned Low Signed High Unsigned High Signed Architecture Data B Result Logic Level Low Unsigned High Signed Low Signed High Signed © December 2009 Altera Corporation ...

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... You can also use embedded multipliers of the Cyclone III device family to implement multiplier adder and multiplier accumulator functions, in which the multiplier portion of the function is implemented using embedded multipliers, and the adder or accumulator function is implemented in logic elements (LEs). © December 2009 Altera Corporation 4–5 Cyclone III Device Handbook, Volume 1 ...

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... Cyclone III Device Handbook, Volume 1 Chapter 4: Embedded Multipliers in the Cyclone III Device Family signa signb aclr clock ena D Q ENA D Q CLRN ENA CLRN D Q ENA CLRN 18 × 18 Multiplier Embedded Multiplier Operational Modes Data Out [35..0] © December 2009 Altera Corporation ...

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... Therefore, all the Data A inputs feeding the same embedded multiplier must have the same sign representation. Similarly, all the Data B inputs feeding the same embedded multiplier must have the same sign representation. © December 2009 Altera Corporation signa signb aclr clock ...

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... Updated “Input Registers” on page 4–4. ■ Updated chapter to new template. Added EP3C120 information. Updated “Introduction” section. ■ Updated Table 4–1 and Table 4–2. ■ Added chapter TOC and “Referenced Documents” section. ■ Initial release. Chapter Revision History © December 2009 Altera Corporation ...

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... Internal logic can also drive GCLKs for internally generated GCLKs and asynchronous clears, clock enables, or other control signals with high fan-out. © December 2009 Altera Corporation 5. Clock Networks and PLLs in the Cyclone III Device Family III device family (Cyclone III and Cyclone III ® ...

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... December 2009 Altera Corporation v — ...

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... EP3C5 and EP3C10 devices only have phase-locked loops (PLLs) 1 and 2. (4) This pin applies only to EP3C5 and EP3C10 devices. (5) Only one of the two CDPCLK pins can feed the clock control block. You can use the other pin as a regular I/O pin. © December 2009 Altera Corporation GCLK Networks (Note 1) 3 ...

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... You can drive the GCLK through logic array routing to enable internal logic elements (LEs) to drive a high fan-out, low-skew signal path. Clock control blocks that have inputs driven by internal logic are not able to drive PLL inputs. © December 2009 Altera Corporation Clock Networks website. ® ...

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... Each PLL generates five clock outputs through the c[4..0] counters. Two of these clocks can drive the GCLK through a clock control block, as shown in f For more information about how to use the clock control block in the Quartus software, refer to the © December 2009 Altera Corporation Clock Control Block Internal Logic DPCLK or CDPCLK C0 C1 ...

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... Remote clock from two clock pins at 5 adjacent edge of (3) device 2 Clock Control 2 Block (1) GCLK[19.. GCLK[19..0] Clock Control Block ( CLK[15..12] DPCLK[3..2] DPCLK[5..4] Clock Networks (Note 1) CDPCLK6 4 PLL 2 CDPCLK5 ( DPCLK7 CLK[7..4] 4 DPCLK6 2 4 (2) (4) CDPCLK4 5 PLL 4 CDPCLK3 © December 2009 Altera Corporation ...

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... You can set the input clock sources and the clkena signals for the GCLK multiplexers through the Quartus II software using the ALTCLKCTRL megafunction. f For more information, refer to the © December 2009 Altera Corporation Figure 5–1 on page 4 Clock Input Pins 5 PLL Outputs ...

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... The clkena signal can also disable clock outputs if the system is not tolerant to frequency overshoot during PLL resynchronization. Cyclone III Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family clkena clkena_out D Q clkin Clock Networks clk_out Figure 5–4. © December 2009 Altera Corporation ...

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... Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family PLLs in the Cyclone III Device Family Altera recommends using the clkena signals when switching the clock source to the PLLs or the GCLK. The recommended sequence is: 1. Disable the primary output clock by deasserting the clkena signal. ...

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... Cyclone III Device Data Sheet VCO chapters. Figure 5–7, without going through the GCLK. Cyclone III Device Family PLL Hardware Overview ÷C0 ÷C1 8 ÷C2 PLL output GCLKs ÷C3 mux External clock output ÷C4 ÷M GCLK networks and © December 2009 Altera Corporation ...

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... Cyclone III device family PLLs can drive out to any regular I/O pin through the GCLK. You can also use the external clock output pins as general purpose I/O pins if external PLL clocking is not required. © December 2009 Altera Corporation PLL # ...

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... Clock input pin to the PLL phase-frequency detector (PFD) input ■ Cyclone III Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family Data pin PLL reference clock at input pin Data at register Clock at register Clock Feedback Modes © December 2009 Altera Corporation ...

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... The Quartus II software timing analyzer reports any phase difference between the two. In normal mode, the PLL fully compensates the delay introduced by the GCLK network. © December 2009 Altera Corporation Phase Aligned PLL Reference Clock at the Input Pin PLL Clock at the ...

Page 78

... External PLL Clock Output Cyclone III Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family Phase Aligned (1) Phase Aligned PLL Reference Clock at the Input Pin PLL Clock at the Output Pin Clock Feedback Modes © December 2009 Altera Corporation ...

Page 79

... ALTPLL megafunction. 1 Phase alignment between output counters are determined using the t specification. © December 2009 Altera Corporation (M/N). Each output port has a unique post-scale counter IN Cyclone III Device Handbook, Volume 1 5–15 PLL_PSERR ...

Page 80

... Combining the programmable duty cycle with programmable phase shift allows the generation of precise non-overlapping clocks. Cyclone III Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family Figure VCO Output C0 VCO Output C1 VCO Output C2 VCO Output C3 VCO Output C4 VCO Output Hardware Features 5–12. © December 2009 Altera Corporation ...

Page 81

... PLL clock outputs are operating at the desired phase and frequency set in the Quartus II MegaWizard 1 Altera recommends that you use the areset and locked signals in your designs to control and observe the status of your PLL. This implementation is illustrated in Figure 5–13. Locked Signal Implementation © ...

Page 82

... Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family II tool to probe the locked signal before the D flip-flop, the ® Switchover Clock State Sense Machine clksw n Counter refclk muxout Hardware Features ALTPLL Megafunction clkbad0 clkbad1 Activeclock clkswitch (provides manual switchover support) PFD fbclk © December 2009 Altera Corporation ...

Page 83

... Figure 5–15. Automatic Switchover Upon Clock Loss Detection Note to Figure 5–15: (1) Switchover is enabled on the falling edge of inclk0 or inclk1, depending on which clock is available. In this figure, switchover is enabled on the falling edge of inclk1. © December 2009 Altera Corporation inclk0 inclk1 (1) muxout clkbad0 clkbad1 activeclock 5– ...

Page 84

... Cyclone III Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family (1) inclk0 inclk1 muxout clkswitch activeclock clkbad0 clkbad1 Hardware Features © December 2009 Altera Corporation ...

Page 85

... VCO locks on to the secondary clock, some overshoot can occur (an over-frequency condition) in the VCO frequency. Figure 5–17. VCO Switchover Operating Frequency ΔF vco © December 2009 Altera Corporation Guide. shows how the VCO frequency gradually decreases when the primary Primary Clock Stops Running Switchover Occurs 5– ...

Page 86

... Cyclone III Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family N 1 ------------- - = ---------------- - - 8f 8Mf VCO 100 MHz and then f REF Programmable Bandwidth Equation 5–1 = 800 MHz, and VCO © December 2009 Altera Corporation ...

Page 87

... The Cyclone III device family supports dynamic phase shifting of VCO phase taps only. The phase shift is configurable for any number of times. Each phase shift takes about one scanclk cycle, allowing you to implement large phase shifts quickly. © December 2009 Altera Corporation Equation 5– – ...

Page 88

... Five Clock Control Blocks Input to PLL CLK[8..11 GCLK[10..14] GCLK[0:19] GCLK[0:19] GCLK[5..9] GCLK[0:19] GCLK[0:19] 20 GCLK[15..19 CLK[12..15] Five Clock Output from PLL Control Blocks PLL Cascading PLL 2 Output from PLL 5 2 Five Clock Control Blocks CLK[4..7] 2 PLL 4 © December 2009 Altera Corporation ...

Page 89

... Figure 5–20. PLL Reconfiguration Scan Chain from M counter from N counter scandata scanclkena configupdate inclk /C4 /C3 scandataout scandone scanclk © December 2009 Altera Corporation ) delays in real time and loop filter components CP PFD LF/K/CP /C2 /C1 /C0 Cyclone III Device Handbook, Volume 1 5–25 F VCO ...

Page 90

... Cyclone III Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family , R, C settings through 5 to reconfigure the PLL any number of times. D0 LSB D0_old © December 2009 Altera Corporation PLL Reconfiguration Dn ...

Page 91

... Cyclone III device family PLLs have a 144-bit scan chain. Table 5–4 lists the number of bits for each component of the PLL. Table 5–4. Cyclone III Device Family PLL Reprogramming Bits (Part Block Name C4 ( © December 2009 Altera Corporation Number of Bits Counter Other (2) ...

Page 92

... Figure 5–23. Scan Chain Bit Order DATAOUT Cyclone III Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family Number of Bits Counter MSB LSB DATAOUT PLL Reconfiguration Other Total 2 ( 144 rbypass rselodd 8 9 © December 2009 Altera Corporation DATAIN ...

Page 93

... Table 5–6. Loop Filter Resistor Value Control LFR[ Table 5–7. Loop Filter Control of High Frequency Capacitor LFC[1] Bypassing PLL Counter Bypassing a PLL counter results in a multiply (M counter divide ( counters) factor of one. © December 2009 Altera Corporation Table 5–5 through Table 5–7 CP[ LFR[3] LFR[ ...

Page 94

... Source Destination PLL Logic array or I/O reconfiguration pins circuit PLL Logic array or I/O reconfiguration pins circuit PLL Logic array or I/O reconfiguration pins circuit PLL GCLK or I/O pins reconfiguration circuit PLL reconfiguration Logic array or circuit I/O pins © December 2009 Altera Corporation ...

Page 95

... All signals are synchronous to scanclk, so they are latched on the scanclk edges and must meet t Figure 5–24. PLL Dynamic Phase Shift phasecounterselect Dynamic phase shifting can be repeated indefinitely. All signals are synchronous to scanclk, so they must meet t © December 2009 Altera Corporation [1] [ ...

Page 96

... For information about PLL specifications, refer to the Cyclone III LS Device Data Sheet Cyclone III Device Handbook, Volume 1 Chapter 5: Clock Networks and PLLs in the Cyclone III Device Family Guide. Cyclone III Device Data Sheet chapters. © December 2009 Altera Corporation Spread-Spectrum Clocking Figure 5–24, and ...

Page 97

... October 2008 2.1 May 2008 2.0 September 2007 1.2 © December 2009 Altera Corporation Changes Made Minor changes to the text. Made minor correction to the part number. Updated to include Cyclone III LS information Updated chapter part number. ■ Updated “Clock Networks” on page 5–1. ...

Page 98

... Added new “Programmable Bandwidth” section with Figure 5–21 and ■ Figure 5–22. Replaced Figure 5-30 with correct diagram. ■ Added chapter TOC and “Referenced Documents” section. ■ Initial release. Chapter Revision History © December 2009 Altera Corporation ...

Page 99

... Refer to each chapter for its own specific revision history. For information about when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook. © January 2010 Altera Corporation Section 2. I/O Interfaces III device family I/O features and ® ...

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...

Page 101

... The I/O capabilities of the Cyclone III device family are driven by the diversification of I/O standards in many low-cost applications, and the significant increase in required I/O performance. Altera’s objective is to create a device that accommodates your key board design needs with ease and flexibility. ...

Page 102

... Open-Drain Out Slew Rate Control ENA ACLR sclr/ /PRN preset D Q ENA ACLR /PRN Input Register I/O Element Features V CCIO V CCIO Programmable Pull-Up Resistor Bus Hold Input Pin to Input Register Delay or Input Pin to Logic Array Delay © December 2009 Altera Corporation ...

Page 103

... The default current setting in the Quartus II software is highlighted in bold italic for 3.3-V LVTTL and 3.3-V LVCMOS I/O standards. f For information about how to interface the Cyclone III device family with 3.3-, 3.0-, or 2.5-V systems, refer to the guidelines provided in Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O © December 2009 Altera Corporation (Note Current Strength Setting (mA ...

Page 104

... Cyclone III Device Handbook, Volume 1 Chapter 6: I/O Features in the Cyclone III Device Family Assignment Editor chapter in volume 2 of the Assignment Editor chapter in volume 2 of the © December 2009 Altera Corporation I/O Element Features ...

Page 105

... Quartus II software for each path. If the pin uses the input register, one of the delays is disregarded and the delay is set with the input delay from pin to input register logic option in the Quartus II software. © December 2009 Altera Corporation Assignment Editor chapter in volume 2 of the voltage level driven through the ...

Page 106

... AN 447: Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems. Cyclone III Device Handbook, Volume 1 Chapter 6: I/O Features in the Cyclone III Device Family chapter in volume 2 of the Quartus II Handbook. Assignment Editor chapter in volume 2 of the © December 2009 Altera Corporation I/O Element Features Area ...

Page 107

... LVTTL/LVCMOS 50, 25 1.5-V LVCMOS 50, 25 1.2-V LVCMOS 50 SSTL-2 Class I 50 SSTL-2 Class II 25 © December 2009 Altera Corporation High-Speed Differential Interfaces in Cyclone III Devices On-Chip Series Termination Without Calibration Setting, in ohms (Ω) Column I/O Row I/O 50, 25 50, 25 50, 25 50, 25 50, 25 ...

Page 108

... Cyclone III Device Family Driver Series Termination V CCIO GND if both banks enable OCT calibration. If CCIO s, only the bank in which the calibration block CCIO OCT Support Setting, in ohms (Ω) Column I — 25 Receiving Device © December 2009 Altera Corporation ...

Page 109

... During calibration, the resistance of the RUP and RDN pins varies. For an estimate of the maximum possible current through the external calibration resistors, assume a minimum resistance of 0 Ω on the RUP and RDN pins during calibration. © December 2009 Altera Corporation I/O Bank 7 I/O Bank 8 Cyclone III Device Family ...

Page 110

... Chapter 6: I/O Features in the Cyclone III Device Family Cyclone III Device Family OCT with Calibration with RUP and RDN pins RUP OCT Calibration V CCIO Circuitry RDN OCT Support V CCIO External Calibration Resistor External Calibration Resistor GND = 50 Ω) for SSTL-2 and S © December 2009 Altera Corporation ...

Page 111

... The Cyclone III device family supports multiple single-ended and differential I/O standards. Apart from 3.3-, 3.0-, 2.5-, 1.8-, and 1.5-V support, the Cyclone III device family also supports 1.2-V I/O standards. © December 2009 Altera Corporation Cyclone III Device Family Driver Series Termination V ...

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... December 2009 Altera Corporation Pins — v — — — — — — — — — — ...

Page 113

... I/O standards do not specify a recommended termination scheme per the JEDEC standard Voltage-Referenced I/O Standard Termination Voltage-referenced I/O standards require an input reference voltage (V termination voltage (V termination voltage of the transmitting device, as shown in © December 2009 Altera Corporation V Level ( CIO Standard Support Input Output — ...

Page 114

... V REF Receiver Transmitter Cyclone III Device V TT Family Series OCT REF Receiver Transmitter (Figure 6–8 and Figure 6–9). Termination Scheme for I/O Standards HSTL Class REF Receiver REF Receiver SSTL Class REF Receiver REF Receiver © December 2009 Altera Corporation ...

Page 115

... Cyclone III Device Family Series OCT 50 50 OCT 50 50 Transmitter Note to Figure 6–9: (1) Only Differential SSTL-2 I/O standard supports Class II output. © December 2009 Altera Corporation Termination Differential HSTL V TT External On-Board Termination Transmitter V TT Cyclone III Device Family Series OCT 50 OCT ...

Page 116

... Bus LVDS ( 7) LVPECL (3) SSTL-2 class I and II SSTL-18 CLass I and II HSTL-18 Class I and II HSTL-15 Class I and II HSTL-12 Class I and II (4) Differential SSTL-2 (5) Differential SSTL-18 (5) Differential HSTL-18 (5) Differential HSTL-15 (5) Differential HSTL-12 (6) I/O Bank 3 I/O Bank 4 I/O Banks chapter. © December 2009 Altera Corporation ...

Page 117

... VREFB1N0 must be powered with 1.25 V, and the remaining VREFB1N[1:3] pins (if available) are used as I/O pins. If multiple V I/O bank, the VREF pins must all be powered by the same voltage level because the VREF pins are shorted together within the same I/O bank. © December 2009 Altera Corporation I/O Banks ...

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... Cyclone III REF I/O Banks Pin Count 144 164 256 144 164 256 144 164 240 256 484 144 240 256 324 240 324 484 780 484 780 484 780 484 780 I/O Banks chapters © December 2009 Altera Corporation ...

Page 119

... LVTTL/LVCMOS systems, you are responsible for managing overshoot or undershoot to stay in the absolute maximum ratings and the recommended operating conditions, provided in the Sheet chapters. 1 The PCI clamping diode is enabled by default in the Quartus II software for input signals with bank V © December 2009 Altera Corporation Pin Count 1 2 278 3 3 278 3 ...

Page 120

... Cyclone III Device Handbook, Volume 1 Chapter 6: I/O Features in the Cyclone III Device Family AN 447: Interfacing Cyclone III Devices with Systems. High-Speed Differential Interfaces in Cyclone III Devices External Memory Interfaces in Cyclone III Devices I/O Banks chapter. © December 2009 Altera Corporation ...

Page 121

... Pad Placement and DC Guidelines Pad Placement and DC Guidelines Pad Placement Altera recommends that you create a Quartus II design, enter your device I/O assignments, and compile your design to validate your pin placement. The Quartus II software checks your pin connections with respect to the I/O assignment and placement rules to ensure proper device operation ...

Page 122

... Updated “V Pad Placement Guidelines” section and added new ■ REF Figure 6–17. Updated Table 6–11. ■ Added new “DCLK Pad Placement Guidelines” section. ■ Updated “DC Guidelines” section. ■ Chapter Revision History © December 2009 Altera Corporation ...

Page 123

... Date Version July 2007 1.1 March 2007 1.0 © December 2009 Altera Corporation Changes Made Updated feetpara note in “Programmable Current Strength” section. ■ Updated feetpara note in “Slew Rate Control” section. ■ Updated feetpara note in “Open-Drain Output” section. ■ ...

Page 124

... Cyclone III Device Handbook, Volume 1 Chapter 6: I/O Features in the Cyclone III Device Family Chapter Revision History © December 2009 Altera Corporation ...

Page 125

... This chapter describes the high-speed differential I/O features and resources in the Cyclone III device family. High-speed differential I/O standards have become popular in high-speed interfaces because of their significant advantages over single-ended I/O standards. The Altera Cyclone III device family (Cyclone III and Cyclone III LS devices) supports LVDS, ® ...

Page 126

... SSTL-18 Class I and II HSTL-18 Class I and II HSTL-15 Class I and II HSTL-12 Class I Differential SSTL-2 (4) Differential SSTL-18 (4) Differential HSTL-18 (4) DIfferential HSTL-15 (4) Differential HSTL-12 (4) I/O Bank 3 I/O Bank 4 I/O banks 3 and 4 also support the HSTL-12 Class II I/O standard High-Speed I/O Interface © December 2009 Altera Corporation ...

Page 127

... The differential interface data serializers and deserializers (SERDES) are automatically constructed in the core logic elements (LEs) with the Quartus software ALTLVDS megafunction. © December 2009 Altera Corporation External Resistor Network at Transmitter 1,2,5,6 ...

Page 128

... FBGA 151 8 UBGA 123 8 FBGA 101 8 FBGA 169 8 UBGA 101 8 FBGA 94 8 FBGA 221 8 High-Speed I/O Interface (Note 1), (2) Clock Total Output 140 140 127 4 227 4 127 4 135 4 163 4 135 4 113 4 181 4 113 4 106 4 233 © December 2009 Altera Corporation ...

Page 129

... Cyclone III devices. Table 7–3. Cyclone III Devices Migratable Differential Channels Package Type E144 M164 Q240 F256 © December 2009 Altera Corporation Number of Differential Channels Package User I/O Clock Input U484 101 F484 101 F780 ...

Page 130

... EP3C55 and EP3C120 EP3C80 and EP3C120 High-Speed I/O Interface (Note 1) (Part Migratable Channels User I/O CLK Total 102 8 110 98 8 106 102 8 110 106 102 8 110 98 8 106 102 8 110 106 144 8 152 142 8 150 160 8 168 © December 2009 Altera Corporation ...

Page 131

... V to 1.8 V based on different frequency ranges. The ANSI/TIA/EIA-644 specification supports an input voltage range 2 For more information about the LVDS I/O standard electrical specifications in the Cyclone III device family, refer to the Device Data Sheet © December 2009 Altera Corporation Migration between Devices User I/O 101 101 71 71 ...

Page 132

... Cyclone III Device Family txout + Cyclone III Device Family Logic Array txout - Input Buffer Output Buffer Resistor Network Ω 100 Ω Ω High-Speed I/O Standards Support Receiving Device rxin + 50 Ω 100 Ω 50 Ω rxin - (Note 1) LVDS Receiver © December 2009 Altera Corporation ...

Page 133

... The maximum data rate achievable depends on many factors. 1 Altera recommends that you perform simulation using the IBIS model while considering factors such as bus loading, termination values, and output and input buffer location on the bus to ensure that the required performance is achieved. ...

Page 134

... Cyclone III Device Family True RSDS, Mini-LVDS, or PPDS Transmitter Cyclone III Device Handbook, Volume 1 Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family High-Speed I/O Standards Support Cyclone III Device Data Sheet chapters. RSDS, Mini-LVDS, or PPDS Receiver 50 100 50 © December 2009 Altera Corporation and ...

Page 135

... Altera recommends that you perform simulations using Cyclone III device family IBIS models to validate that custom resistor values meet the RSDS, mini-LVDS, or PPDS requirements. You can use a single external resistor instead of using three resistors in the resistor network for an RSDS interface, as shown in solution reduces the external resistor count while still achieving the required signaling level for RSDS ...

Page 136

... Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family Single Resistor Network 50 Ω 100 Ω Ω and Cyclone III LS Device Data Sheet (Figure 7–9). 0.1 µ ICM 0.1 µF High-Speed I/O Standards Support RSDS Receiver chapters. Cyclone III Device Family LVPECL Receiver © December 2009 Altera Corporation ...

Page 137

... Cyclone III Device I/O Features Cyclone III LS Device Data Sheet Figure 7–10 shows the differential SSTL Class I interface. Figure 7–10. Differential SSTL Class I Interface Output Buffer © December 2009 Altera Corporation Cyclone III Device Family LVPECL Receiver 50 100 50 to which termination resistors are ...

Page 138

... Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family which termination resistors are connected. CCIO Features, Cyclone III Device Data Ω Ω Ω High-Speed I/O Standards Support V TT Receiver Sheet, and Cyclone III LS Device 50 Ω Receiver © December 2009 Altera Corporation ...

Page 139

... The overshoot produced by this extra switching current is different from the overshoot caused by signal reflection. This overshoot happens only during switching, and does not produce ringing. Figure 7–14 shows the differential output signal with pre-emphasis. Figure 7–14. The Output Signal with Pre-Emphasis © December 2009 Altera Corporation Ω ...

Page 140

... Allowed input jitter on the input clock to the PLL that is tolerable — while maintaining PLL lock. — Peak-to-peak output jitter from the PLL. Time Unit Interval (TUI) TCCS RSKM RSKM Sampling Window (SW) High-Speed I/O Timing Figure 7–15. Description ) TCCS © December 2009 Altera Corporation ...

Page 141

... Longer traces have more inductance and capacitance. These traces must be as short as possible to limit signal integrity issues. Place termination resistors as close to receiver input pins as possible. ■ © December 2009 Altera Corporation (Note 1) 0.5 × TCCS RSKM SW × RSKM TCCS ...

Page 142

... Quartus II software megafunction because they do not have a dedicated circuit for the SERDES. The Cyclone III device family uses the I/O registers and LE registers to improve the timing performance and support the SERDES. Altera Quartus II software allows you to design your high-speed interfaces using the ALTLVDS megafunction ...

Page 143

... July 2009 3.1 June 2009 3.0 October 2008 1.3 © December 2009 Altera Corporation Changes Made Minor changes to the text. Made minor correction to the part number. Updated to include Cyclone III LS information Updated chapter part number. ■ Updated “Introduction” on page 7–1, “High-Speed I/O Interface” on ■ ...

Page 144

... Updated (Note 3) to Table 7–1. ■ Added new Table 7–3. ■ Added (Note 1) to Figure 7–21. ■ Added (Note 1) to Figure 7–23. ■ Added chapter TOC and “Referenced Documents” section. ■ Initial release. Chapter Revision History © December 2009 Altera Corporation ...

Page 145

... Altera DDR2 or DDR SDRAM memory controllers, third-party controllers custom controller for unique application needs. Cyclone III device family supports QDR II interfaces electrically, but Altera does not supply controller or physical layer (PHY) megafunctions for QDR II interfaces. This chapter includes a description of the hardware interfaces for external memory interfaces available in Cyclone III device family ...

Page 146

... Cyclone III device family does not support differential strobe pins, which is an optional feature in the DDR2 SDRAM device. f When you use the Altera Memory Controller MegaCore you. For more information about the memory interface data path, refer to External Memory 1 ALTMEMPHY is a self-calibrating megafunction, enhanced to simplify the implementation of the read-data path in different memory interfaces ...

Page 147

... EQFP(1) EP3C5 164-pin MBGA (1) 256-pin FineLine BGA/256-pin Ultra FineLine BGA (1) 144-pin EQFP (1) EP3C10 164-pin MBGA (1) 256-pin FineLine BGA/256-pin Ultra FineLine BGA (1) © January 2010 Altera Corporation Number Number Side ×8 ×9 Groups Groups Left 0 0 Right 0 0 Top ( Bottom (3), ...

Page 148

... January 2010 Altera Corporation ...

Page 149

... BGA/484-pin Ultra FineLine BGA 780-pin FineLine BGA 484-pin FineLine BGA/484-pin Ultra FineLine BGA EP3C55 780-pin FineLine BGA 484-pin FineLine BGA/484-pin Ultra FineLine BGA EP3C80 780-pin FineLine BGA © January 2010 Altera Corporation Number Number Side ×8 ×9 Groups Groups Left (4), ( Right (3), ...

Page 150

... Number Number Number Number ×16 ×18 ×32 ×36 Groups Groups Groups Groups (Note 1) (Part Number Number Number Number of ×16 of ×18 of ×32 of ×36 Groups Groups Groups Groups 1 1 — — — — — — — — © January 2010 Altera Corporation ...

Page 151

... Y denotes whether the group is located on the top (T), bottom (B), left (L) or right (R) side of the device. For example, DQS2T indicates a DQS pin belonging to group 2, located on the top side of the device. Similarly, the DQ pins belonging to that group is shown as DQ2T. © January 2010 Altera Corporation Number Number Side of × ...

Page 152

... Chapter 8: External Memory Interfaces in the Cyclone III Device Family Cyclone III Device Family Memory Interfaces Pin Support II software issues an error message group is not placed properly (Note 1) I/O Bank 8 I/O Bank 7 Cyclone III Device Family I/O Bank 3 I/O Bank 4 DQS2R/CQ3R DQS0R/CQ1R DQS1R/CQ1R# DQS3R/CQ3R# © January 2010 Altera Corporation ...

Page 153

... In Cyclone III device family, the DM pins are preassigned in the device pinouts. The Quartus II Fitter treats the DQ and DM pins in a DQS group equally for placement purposes. The preassigned DQ and DM pins are the preferred pins to use. © January 2010 Altera Corporation I/O Bank 8 I/O Bank 7 ...

Page 154

... DQ pin. These LE registers are located in the logic array block (LAB) adjacent to the DDR input pin. Cyclone III Device Handbook, Volume 1 Chapter 8: External Memory Interfaces in the Cyclone III Device Family Cyclone III Device Family Memory Interfaces Features © January 2010 Altera Corporation ...

Page 155

... Because the read-capture clock is generated by the PLL, the read-data strobe signal (DQS or CQ) is not used during read operation in Cyclone III device family; hence, postamble is not a concern in this case. © January 2010 Altera Corporation DDR Input Registers in Cyclone III Device Family LE Register ...

Page 156

... DDR Output Enable Registers IOE Register Output Enable Register A OE data1 data0 IOE Register Output Enable Register B OE DDR Output Registers IOE Register data0 Output Register A O data1 IOE Register ® Output Register B O chapter DQS © January 2010 Altera Corporation ...

Page 157

... The PLL is instantiated in the ALTMEMPHY megafunction. All outputs of the PLL are used when the ALTMEMPHY megafunction is instantiated to interface with external memories. f For more information about the usage of PLL outputs by the ALTMEMPHY megafunction, refer to © January 2010 Altera Corporation Delay Half a Clock ...

Page 158

... Updated (Note 1) to Figure 8-4. Updated Figure 8–5 and 8–14. ■ Updated “Data and Data Clock/Strobe Pins” section. ■ Updated Table 8–5. ■ Added chapter TOC and “Referenced Documents” section. ■ Initial release. Chapter Revision History Clock Networks . © January 2010 Altera Corporation ...

Page 159

... Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the complete handbook. © December 2009 Altera Corporation Section 3. System Integration Cyclone III Device Handbook, Volume 1 ...

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...

Page 161

... This chapter also includes configuration pin descriptions and the Cyclone III device family configuration file formats. In this chapter, the generic term “device” includes all Cyclone III device family. © December 2009 Altera Corporation 9. Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family III devices. The Cyclone III device family (Cyclone III and ® ...

Page 162

... Download Cable External Host with — Flash Memory External Host with — Flash Memory Download Cable — “Remote System Upgrade” on Table 9–11 on page © December 2009 Altera Corporation Configuration Features Remote Design System Security Upgrade (Cyclone III LS (1) Devices Only) v ...

Page 163

... In PS mode, use the Cyclone III device family decompression feature to reduce configuration time. 1 Altera recommends using the Cyclone III device family decompression feature during AS configuration if you must save configuration memory space in the serial configuration device. When you enable compression, the Quartus II software generates configuration files with compressed configuration data ...

Page 164

... In the Convert Programming Files dialog box, select the .pof you added to SOF Data and click Properties the SOF File Properties dialog box, turn on the Compression option. Cyclone III Device Handbook, Volume 1 Configuration Features (Figure 9–1). © December 2009 Altera Corporation ...

Page 165

... Table 9–2. Cyclone III Device Family Supported POR Times Across Configuration Schemes Configuration Scheme Fast Active Serial Standard (AS Standard POR) Fast Active Serial Standard (AS Standard POR) Fast Active Serial Fast (AS Fast POR) Fast Active Serial Fast (AS Fast POR) © December 2009 Altera Corporation Serial Data Uncompressed V CC Decompression 10 kΩ ...

Page 166

... Notes to Table 9–2: (1) Altera recommends connecting the MSEL pins to V (2) The configuration voltage standard is applied to the V (3) JTAG-based configuration takes precedence over other configuration schemes, which means the MSEL pin settings are ignored. However, the POR time is dependent on the MSEL pin settings. ...

Page 167

... TDO and TDI pin or the serial configuration device for the DATA[0]pin. When cascading Cyclone III device family in a multi-device configuration, you must connect the repeater buffers between the master and slave devices for DATA and DCLK. © December 2009 Altera Corporation Device EP3C5 EP3C10 EP3C16 ...

Page 168

... R (1) O Configuration Process This section describes the configuration process. f For more information about the configuration cycle state machine of Altera refer to the Configuring Altera FPGAs Handbook. Power Up If the device is powered up from the power-down state, the V must be powered up to the appropriate level for the device to exit POR. ...

Page 169

... You can turn on the Enable user-supplied start-up clock (CLKUSR) option in the Quartus II software from the General tab of the Device and Pin Options dialog box. When you turn on © December 2009 Altera Corporation Cyclone III Device Data Sheet chapters. Cyclone III Device Handbook, Volume 1 9– ...

Page 170

... Cyclone III Device Handbook, Volume 1 Initialization Clock Cycles 3,185 3,192 ) for Cyclone III device family. MAX f (MHz) MAX 133 100 Table 9–7. . The MSEL[3..0] pins have 9-kΩ internal CCINT © December 2009 Altera Corporation Configuration Features ...

Page 171

... Fast Passive Parallel Fast (FPP Fast POR) (for Cyclone III LS devices only) Fast Passive Parallel Fast (FPP Fast POR) with Encryption (for Cyclone III LS devices only) © December 2009 Altera Corporation Table 9–7. or GND without any pull-up or pull-down resistors CCA (Note 1) ...

Page 172

... The JTAG-based configuration takes precedence over other configuration schemes, which means the MSEL pin settings are ignored. (6) Do not leave the MSEL pins floating. Connect them to V Altera recommends connecting the MSEL pins to GND if your device is only using the JTAG configuration. AS Configuration (Serial Configuration Devices) In the AS configuration scheme, Cyclone III device family is configured using a serial configuration device ...

Page 173

... EPCS1 does not support Cyclone III device family because of its insufficient memory capacity. Table 9–8 lists the AS DCLK output frequency for Cyclone III device family. Table 9–8. AS DCLK Output Frequency Oscillator 40 MHz © December 2009 Altera Corporation V (1) V (1) CCIO CCIO V ...

Page 174

... Cyclone III Device Handbook, Volume 1 timing parameters are identical to the timing parameters for PS CD2UM Table 9–13 on page 9–39. level to help the internal weak pull-up resistor. When the first CCIO Configuration Features , CF2CD CF2ST0 CFG (Figure 9–4). © December 2009 Altera Corporation ...

Page 175

... JTAG Pin I/O Requirements” on page (8) The 50-Ω series resistors are optional if the 3.3-V configuration voltage standard is applied. For optimal signal integrity, connect these 50-Ω series resistors if the 2.5- or 3.0-V configuration voltage standard is applied. © December 2009 Altera Corporation V CCIO (1) V CCIO (2) kΩ ...

Page 176

... You must connect its MSEL pins to select the AS configuration scheme. The remaining Cyclone III device family is configuration slaves and you must connect their MSEL pins to select the PS configuration scheme. Any other Altera device that supports PS configuration can also be part of the chain as a configuration slave. 1 When connecting a serial configuration device to the Cyclone III device family in the multi-device AS configuration, you must connect a 25-Ω ...

Page 177

... In this configuration method, you can either compress or uncompress the .sofs. 1 You can still use this method if the master and slave devices use the same .sof. © December 2009 Altera Corporation Figure 9–4 on page Figure 9–5. The first device is the master device and its MSEL Figure 9– ...

Page 178

... Slave Device of the Cyclone III Device Family nSTATUS CONF_DONE nCONFIG N.C. (3) nCE nCEO DATA[0] DCLK MSEL[3..0] (4) Slave Device of the Cyclone III Device Family nSTATUS CONF_DONE nCONFIG N.C. (3) nCE nCEO DATA[0] DCLK MSEL[3..0] (4) Table 9–7 on “Configuration and JTAG Pin I/O © December 2009 Altera Corporation ...

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... Cyclone III device family unconnected or use the nCEO output pins as normal user I/O pins. The DATA and DCLK pins are connected in parallel to all the Cyclone III device family. © December 2009 Altera Corporation where the master is set mode and the slave devices are Figure 9–6. ...

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... Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family Altera recommends putting a buffer before the DATA and DCLK output from the master device to avoid signal strength and integrity issues. The buffer must not significantly change the DATA-to-DCLK relationships or delay them with respect to other AS signals (ASDI and nCS) ...

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... The existing diodes and capacitors are sufficient. Altera has developed the Serial FlashLoader (SFL), a JTAG-based in-system programming solution for Altera serial configuration devices. The SFL is a bridge design for the Cyclone III device family that uses its JTAG interface to access the EPCS JIC (JTAG Indirect Configuration Device Programming) file and then uses the AS interface to program the EPCS device ...

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... For effective voltage clamping, Altera recommends using the Schottky diode, which has a relatively lower forward diode voltage (VF) than the switching and Zener diodes. For more information about the interface guidelines using Schottky diodes, refer to Devices ...

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... In production environments, serial configuration devices are programmed using multiple methods. Altera programming hardware or other third-party programming hardware is used to program blank serial configuration devices before they are mounted onto PCBs. Alternatively, you can use an on-board microprocessor to program the serial configuration device in-system by porting the reference C-based SRunner software driver provided by Altera ...

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... You must refer to the respective flash data sheets to check for supported speed grades and package options. Cyclone III Device Handbook, Volume 1 Embedded Memory P30 flash family and the Numonyx ® Numonyx P30 Flash Family (2) Numonyx P33 Flash Family © December 2009 Altera Corporation Configuration Features ( ...

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... Cyclone III device and the flash memory. The following are the control signals from the Cyclone III device to flash memory: ■ DCLK ■ nRESET ■ FLASH_nCE ■ nOE ■ nAVD ■ nWE © December 2009 Altera Corporation 9–25 Cyclone III Device Handbook, Volume 1 ...

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... Cyclone III devices must follow the recommendations listed you use the AP configuration scheme for Cyclone III devices, the and 8 must be 3.3, 3.0, 2.5, or 1.8 V. Altera does not recommend using the level shifter between the Numonyx P30/P33 flash and the Cyclone III device in the AP configuration scheme. 1 There are no series resistors required in the AP configuration mode for Cyclone III devices when using the Numonyx flash at 2 ...

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... Connect its MSEL pins to select the AP configuration scheme. The remaining Cyclone III devices are used as configuration slaves. Connect their MSEL pins to select the FPP configuration scheme. Any other Altera device that supports FPP configuration can also be part of the chain as a configuration slave. ...

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... MSEL[3..0] MSEL[3..0] (4) DQ[7..0] DATA[7..0] DCLK Cyclone III Slave Device or GND. CCA Configuration Features V CCIO (2) 10 kΩ N.C. (3) nCE nCEO MSEL[3..0] (4) (4) DQ[7..0] DATA[7..0] DCLK Cyclone III Slave Device Table 9–7 on “Configuration © December 2009 Altera Corporation ...

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... JTAG Pin I/O Requirements” on page 9– multi-device AP configuration, the board trace length between the parallel flash and the master device must follow the recommendations listed in © December 2009 Altera Corporation V CCIO (1) V CCIO (1) V CCIO (1) V CCIO (2) V CCIO (2) ...

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... Cyclone III Device Handbook, Volume 1 Figure 9–9 and Figure 9–10, the nSTATUS and CONF_DONE pins on all Table 9–12. These recommendations also apply Maximum Board Trace Length from the Cyclone III Device to the Flash Device (Inches Configuration Features Maximum Board Load (pF © December 2009 Altera Corporation ...

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... The other master device must fit the maximum overshoot equation outlined in (7) The other master device can pulse nCONFIG under system control rather than tied to V © December 2009 Altera Corporation Other Master Device (6) V CCIO (1) ...

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... Altera does not recommend M to exceed six inches as listed in (2) Altera recommends using a balanced star routing. Try to keep the N length equal and as short as possible to minimize reflection noise from the transmission line. The M length is applicable for this setup. Estimating the AP Configuration Time AP configuration time is dominated by the time it takes to transfer data from the parallel flash to the Cyclone III devices ...

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... APFC_BOOT_ADDR JTAG instruction. For more information about the APFC_BOOT_ADDR JTAG instruction, refer to Instructions” on page © December 2009 Altera Corporation AN 478: Using FPGA-Based Parallel Flash Loader Software. 9–13. You can change the default configuration default boot address 9– ...

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... AN 386: Using the Parallel Flash Loader Software. Configuration Features Top Parameter Flash Memory 128-Kbit parameter area Other data/code Boot Configuration Data Other data/code 16-bit word bit[15] bit[0] © December 2009 Altera Corporation ...

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... When initialization is complete, the device enters user mode. In user mode, the user I/O pins no longer have weak pull-up resistors and function as assigned in your design. © December 2009 Altera Corporation Cyclone III Memory V CCIO (1) V CCIO (1) ...

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... Connect the MSEL pins directly to V “Configuration and JTAG Pin I/O Requirements” on page Configuration Features 9–42). No maximum DCLK V CCIO (2) Cyclone III Device Family (4) (4) MSEL[3..0] CONF_DONE nSTATUS nCE nCEO N.C. (3) DATA[0] (5) nCONFIG DCLK (5) or ground. CCA 9–7. © December 2009 Altera Corporation ...

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... Ensure that the DCLK and DATA lines are buffered. Devices must be of the same density and package. All devices start and complete configuration at the same time. © December 2009 Altera Corporation 9–37 Cyclone III Device Handbook, Volume 1 ...

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... Connect the MSEL pins directly to V “Configuration and JTAG Pin I/O Requirements” on page Configuration Features Cyclone III Device Family (3) MSEL[3..0] (3) CONF_DONE nSTATUS N.C. (2) N.C. (2) nCE nCEO GND DATA[0] (4) nCONFIG DCLK (4) or ground. CCA 9–7. © December 2009 Altera Corporation ...

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... DCLK ST2C K t Data setup time before rising edge on DSU t Data hold time after rising edge DCLK high time CH t DCLK low time CL t DCLK period CLK © December 2009 Altera Corporation (Note 1) t CF2ST1 t CFG t nCONFIG CF2CK t STATUS t CF2ST0 t CLK ...

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... For more information about the initialization clock cycles required in Cyclone III device family, refer to PS Configuration Using a Download Cable In this section, the generic term "download cable" includes the Altera USB-Blaster universal serial bus (USB) port download cable, MasterBlaster™ serial/USB communications cable, ByteBlaster II parallel port download cable, the ByteBlasterMV™ ...