EP2C5T144I8N Altera, EP2C5T144I8N Datasheet - Page 148

IC CYCLONE II FPGA 5K 144-TQFP

EP2C5T144I8N

Manufacturer Part Number
EP2C5T144I8N
Description
IC CYCLONE II FPGA 5K 144-TQFP
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet

Specifications of EP2C5T144I8N

Number Of Logic Elements/cells
4608
Number Of Labs/clbs
288
Total Ram Bits
119808
Number Of I /o
89
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
144-TQFP, 144-VQFP
Family Name
Cyclone® II
Number Of Logic Blocks/elements
4608
# I/os (max)
89
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
4608
Ram Bits
119808
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-2139

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Timing Specifications
5–58
Cyclone II Device Handbook, Volume 1
Note to
(1)
TCCS
Output
jitter (peak
to peak)
t
t
t
R I S E
F A L L
L O C K
Table 5–48. RSDS Transmitter Timing Specification (Part 2 of 2)
Symbol
These specifications are for a three-resistor RSDS implementation. For single-resistor RSDS in ×10 through ×2
modes, the maximum data rate is 170 Mbps and the corresponding maximum input clock frequency is 85 MHz.
For single-resistor RSDS in ×1 mode, the maximum data rate is 170 Mbps, and the maximum input clock frequency
is 170 MHz. For more information about the different RSDS implementations, refer to the
Interfaces in Cyclone II Devices
Table
20–80%,
C
80–20%,
C
5–48:
L O A D
L O A D
Conditions
= 5 pF
= 5 pF
In order to determine the transmitter timing requirements, RSDS receiver
timing requirements on the other end of the link must be taken into
consideration. RSDS receiver timing parameters are typically defined as
t
specifications are t
for the timing budget.
The AC timing requirements for RSDS are shown in
Min
SU
–6 Speed Grade
chapter of the Cyclone II Device Handbook.
and t
Typ
500
500
H
requirements. Therefore, the transmitter timing parameter
Max(1)
200
500
100
CO
(minimum) and t
Min
–7 Speed Grade
Typ
500
500
Max(1)
500
100
200
CO
(maximum). Refer to
Min
–8 Speed Grade
Typ
500
500
High-Speed Differential
Figure
Altera Corporation
Max(1)
February 2008
500
100
200
5–5.
Figure 5–4
Unit
ps
ps
ps
ps
μs

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