EP1K30QC208-3N Altera, EP1K30QC208-3N Datasheet - Page 32

IC ACEX 1K FPGA 30K 208-PQFP

EP1K30QC208-3N

Manufacturer Part Number
EP1K30QC208-3N
Description
IC ACEX 1K FPGA 30K 208-PQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet

Specifications of EP1K30QC208-3N

Number Of Logic Elements/cells
1728
Number Of Labs/clbs
216
Total Ram Bits
24576
Number Of I /o
147
Number Of Gates
119000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Family Name
ACEX™ 1K
Number Of Usable Gates
30000
Number Of Logic Blocks/elements
1728
# I/os (max)
147
Frequency (max)
200MHz
Process Technology
CMOS
Operating Supply Voltage (typ)
2.5V
Logic Cells
1728
Ram Bits
24576
Device System Gates
119000
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1836
EP1K30QC208-3N

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0
ACEX 1K Programmable Logic Device Family Data Sheet
32
OE0
OE1
OE2
OE3
OE4
OE5
CLKENA0/CLK0/GLOBAL0
CLKENA1/OE6/GLOBAL1
CLKENA2/CLR0
CLKENA3/OE7/GLOBAL2
CLKENA4/CLR1
CLKENA5/CLK1/GLOBAL3
Table 7. Peripheral Bus Sources for ACEX Devices
Peripheral Control Signal
When dedicated inputs drive non-inverted and inverted peripheral clears,
clock enables, and output enables, two signals on the peripheral control
bus will be used.
Table 7
the output enable, clock enable, clock, and clear signals share
12 peripheral control signals.
global signals.
Signals on the peripheral control bus can also drive the four global signals,
referred to as GLOBAL0 through GLOBAL3. An internally generated signal
can drive a global signal, providing the same low-skew, low-delay
characteristics as a signal driven by an input pin. An LE drives the global
signal by driving a row line that drives the peripheral bus which then
drives the global signal. This feature is ideal for internally generated clear
or clock signals with high fan-out. However, internally driven global
signals offer no advantage over the general-purpose interconnect for
routing data signals.
The chip-wide output enable pin is an active-high pin that can be used to
tri-state all pins on the device. This option can be set in the Altera
software. The built-in I/O pin pull-up resistors (which are active during
configuration) are active when the chip-wide output enable pin is
asserted. The registers in the IOE can also be reset by the chip-wide reset
pin.
lists the sources for each peripheral control signal and shows how
EP1K10
Row A
Row A
Row B
Row B
Row C
Row C
Row A
Row A
Row B
Row B
Row C
Row C
EP1K30
Row A
Row B
Row C
Row D
Row E
Row A
Row B
Row C
Row D
Row E
Row F
Row F
Table 7
also shows the rows that can drive
EP1K50
Row D
Row H
Row C
Row G
Row A
Row B
Row F
Row A
Row E
Row J
Row J
Row I
Altera Corporation
EP1K100
Row G
Row A
Row C
Row E
Row K
Row D
Row B
Row H
Row L
Row F
Row J
Row I

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