EP1C6T144C7N Altera, EP1C6T144C7N Datasheet - Page 66
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EP1C6T144C7N
Manufacturer Part Number
EP1C6T144C7N
Description
IC CYCLONE FPGA 5980 LE 144-TQFP
Manufacturer
Altera
Series
Cyclone®r
Datasheet
1.EP1C3T144C8.pdf
(106 pages)
Specifications of EP1C6T144C7N
Number Of Logic Elements/cells
5980
Number Of Labs/clbs
598
Total Ram Bits
92160
Number Of I /o
98
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
144-TQFP, 144-VQFP
Family Name
Cyclone®
Number Of Logic Blocks/elements
5980
# I/os (max)
98
Frequency (max)
320.1MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
5980
Ram Bits
92160
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
144
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1816
EP1C6T144C7N
EP1C6T144C7N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1C6T144C7N
Manufacturer:
ALTERA
Quantity:
23
Company:
Part Number:
EP1C6T144C7N
Manufacturer:
ALT
Quantity:
5 510
Company:
Part Number:
EP1C6T144C7N
Manufacturer:
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Quantity:
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Part Number:
EP1C6T144C7N
Manufacturer:
ALTERA
Quantity:
20 000
Cyclone Device Handbook, Volume 1
3–4
Preliminary
Figure 3–1
Figure 3–1. Cyclone JTAG Waveforms
Table 3–4
devices.
t
t
t
t
t
t
t
t
t
t
t
t
t
Captured
Symbol
J C P
J C H
J C L
J P S U
J P H
J P C O
J P Z X
J P X Z
J S S U
J S H
J S C O
J S Z X
J S X Z
Table 3–4. Cyclone JTAG Timing Parameters and Values
Driven
Signal
Signal
to Be
to Be
TMS
TDO
TCK
TDI
shows the JTAG timing parameters and values for Cyclone
TCK
TCK
TCK
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
shows the timing requirements for the JTAG signals.
clock period
clock high time
clock low time
t
JCH
t
t
JPZX
JSZX
t
JCP
t
JSSU
t
JCL
Parameter
t
JSH
t
t
JPCO
JSCO
t
JPSU
t
t
JSXZ
JPH
Altera Corporation
Min
100
50
50
20
45
20
45
—
—
—
—
—
—
t
JPXZ
Max Unit
25
25
25
35
35
35
—
—
—
—
—
—
—
May 2008
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns