EP1K30FC256-3N Altera, EP1K30FC256-3N Datasheet - Page 45

IC ACEX 1K FPGA 30K 256-FBGA

EP1K30FC256-3N

Manufacturer Part Number
EP1K30FC256-3N
Description
IC ACEX 1K FPGA 30K 256-FBGA
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet

Specifications of EP1K30FC256-3N

Number Of Logic Elements/cells
1728
Number Of Labs/clbs
216
Total Ram Bits
24576
Number Of I /o
171
Number Of Gates
119000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
256-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
544-1832
EP1K30FC256-3N

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Generic Testing
Operating
Conditions
V
V
V
I
T
T
T
Symbol
OUT
Table 18. ACEX 1K Device Absolute Maximum Ratings
STG
AMB
J
CCINT
CCIO
I
Supply voltage
DC input voltage
DC output current, per pin
Storage temperature
Ambient temperature
Junction temperature
Parameter
Each ACEX 1K device is functionally tested. Complete testing of each
configurable static random access memory (SRAM) bit and all logic
functionality ensures 100% yield. AC test measurements for ACEX 1K
devices are made under conditions equivalent to those shown in
Figure
all stages of the production flow.
Figure 21. ACEX 1K AC Test Conditions
Tables 18
recommended operating conditions, DC operating conditions, and
capacitance for 2.5-V ACEX 1K devices.
Power supply transients can affect AC
measurements. Simultaneous transitions of
multiple outputs should be avoided for
accurate measurement. Threshold tests
must not be performed under AC
conditions. Large-amplitude, fast-ground-
current transients normally occur as the
device outputs discharge the load
capacitances. When these transients flow
through the parasitic inductance between
the device ground pin and the test system
ground, significant reductions in
observable noise immunity can result.
Numbers in brackets are for 2.5-V devices
or outputs. Numbers without brackets are
for 3.3-V devices or outputs.
21. Multiple test patterns can be used to configure devices during
through
With respect to ground
No bias
Under bias
PQFP, TQFP, and BGA packages, under
bias
21
ACEX 1K Programmable Logic Device Family Data Sheet
provide information on absolute maximum ratings,
Conditions
Note (1)
(2)
Device
Output
Device input
rise and fall
times < 3 ns
8.06 k
[481
[481
703
]
]
–0.5
–0.5
–2.0
Min
–25
–65
–65
C1 (includes
JIG capacitance)
Max
5.75
150
135
135
3.6
4.6
25
To Test
System
VCCIO
Unit
mA
°
°
°
V
V
V
C
C
C
45
13

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