EPF6016ATC100-3 Altera, EPF6016ATC100-3 Datasheet - Page 21

• Manufacturer Part Number: EPF6016ATC100-3
• Description: IC FLEX 6000 FPGA 16K 100-TQFP
• Manufacturer: Altera
• Series: FLEX 6000r

Specifications of EPF6016ATC100-3

• Number Of Logic Elements/cells: 1320
• Number Of Labs/clbs: 132
• Number Of I /o: 81
• Number Of Gates: 16000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Family Name: FLEX 6000
• Number Of Usable Gates: 16000
• Number Of Logic Blocks/elements: 1320
• # Registers: 1320
• # I/os (max): 81
• Frequency (max): 142.86MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 3.3V
• Logic Cells: 1320
• Device System Gates: 16000
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Total Ram Bits: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1274

Altera Corporation
Table 5
each FLEX 6000 device.
In addition to general-purpose I/O pins, FLEX 6000 devices have four
dedicated input pins that provide low-skew signal distribution across the
device. These four inputs can be used for global clock and asynchronous
clear control signals. These signals are available as control signals for all
LEs in the device. The dedicated inputs can also be used as general-
purpose data inputs because they can feed the local interconnect of each
LAB in the device. Using dedicated inputs to route data signals provides
a fast path for high fan-out signals.
The local interconnect from LABs located at either end of two rows can
drive a global control signal. For instance, in an EPF6016 device, LABs C1,
D1, C22, and D22 can all drive global control signals. When an LE drives
a global control signal, the dedicated input pin that drives that signal
cannot be used. Any LE in the device can drive a global control signal by
driving the FastTrack Interconnect into the appropriate LAB. To minimize
delay, however, the Altera software places the driving LE in the
appropriate LAB. The LE-driving-global signal feature is optimized for
speed for control signals; regular data signals are better routed on the
FastTrack Interconnect and do not receive any advantage from being
routed on global signals. This LE-driving-global control signal feature is
controlled by the designer and is not used automatically by the Altera
software. See
Table 5. FLEX 6000 FastTrack Interconnect Resources
EPF6010A
EPF6016
EPF6016A
EPF6024A
Device
summarizes the FastTrack Interconnect resources available in
Figure
FLEX 6000 Programmable Logic Device Family Data Sheet
Rows
11.
4
6
7
Channels per
Row
144
144
186
Columns
22
22
28
Channels per
Column
20
20
30
21