EPF6016ATC100-3 Altera, EPF6016ATC100-3 Datasheet - Page 40

• Manufacturer Part Number: EPF6016ATC100-3
• Description: IC FLEX 6000 FPGA 16K 100-TQFP
• Manufacturer: Altera
• Series: FLEX 6000r

Specifications of EPF6016ATC100-3

• Number Of Logic Elements/cells: 1320
• Number Of Labs/clbs: 132
• Number Of I /o: 81
• Number Of Gates: 16000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Family Name: FLEX 6000
• Number Of Usable Gates: 16000
• Number Of Logic Blocks/elements: 1320
• # Registers: 1320
• # I/os (max): 81
• Frequency (max): 142.86MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 3.3V
• Logic Cells: 1320
• Device System Gates: 16000
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Total Ram Bits: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1274

FLEX 6000 Programmable Logic Device Family Data Sheet
Notes to tables:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
40
t
t
t
t
t
t
t
t
t
t
t
t
t
REG_TO_REG
CASC_TO_REG
CARRY_TO_REG
DATA_TO_REG
CASC_TO_OUT
CARRY_TO_OUT
DATA_TO_OUT
REG_TO_OUT
SU
H
INSU
INH
OUTCO
Table 23. External Timing Parameters
Table 24. LE Timing Microparameters for EPF6010A & EPF6016A Devices (Part 1 of 2)
Symbol
Parameter
Microparameters are timing delays contributed by individual architectural elements and cannot be measured
explicitly.
Operating conditions:
V
V
V
Operating conditions:
V
V
Operating conditions:
V
These parameters are worst-case values for typical applications. Post-compilation timing simulation and timing
analysis are required to determine actual worst-case performance.
This timing parameter shows the delay of a register-to-register test pattern and is used to determine speed grades.
There are 12 LEs, including source and destination registers. The row and column interconnects between the
registers vary in length.
This timing parameter is shown for reference and is specified by characterization.
This timing parameter is specified by characterization.
CCIO
CCIO
CCIO
CCIO
CCIO
CCIO
= 5.0 V ± 5% for commercial use in 5.0-V FLEX 6000 devices.
= 5.0 V ± 10% for industrial use in 5.0-V FLEX 6000 devices.
= 3.3 V ± 10% for commercial or industrial use in 3.3-V FLEX 6000 devices.
= 3.3 V ± 10% for commercial or industrial use in 5.0-V FLEX 6000 devices.
= 2.5 V ± 0.2 V for commercial or industrial use in 3.3-V FLEX 6000 devices.
= 2.5 V, 3.3 V, or 5.0 V.
Setup time with global clock at LE register
Hold time with global clock at LE register
Clock-to-output delay with global clock with LE register using FastFLEX I/O
pin
Min
0.9
1.4
Tables 24
EPF6016A devices.
-1
Max
1.2
0.9
0.9
1.1
1.3
1.6
1.7
0.4
through
Parameter
28
Min
1.0
1.7
Speed Grade
show the timing information for EPF6010A and
-2
Max
1.3
1.0
1.0
1.2
1.4
1.8
2.0
0.4
Min
1.3
2.1
-3
Max
1.7
1.2
1.2
1.5
1.8
2.3
2.5
0.5
Altera Corporation
(8)
(8)
(8)
Conditions
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns