EPF6016ATC100-3 Altera, EPF6016ATC100-3 Datasheet - Page 9

• Manufacturer Part Number: EPF6016ATC100-3
• Description: IC FLEX 6000 FPGA 16K 100-TQFP
• Manufacturer: Altera
• Series: FLEX 6000r

Specifications of EPF6016ATC100-3

• Number Of Logic Elements/cells: 1320
• Number Of Labs/clbs: 132
• Number Of I /o: 81
• Number Of Gates: 16000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Family Name: FLEX 6000
• Number Of Usable Gates: 16000
• Number Of Logic Blocks/elements: 1320
• # Registers: 1320
• # I/os (max): 81
• Frequency (max): 142.86MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 3.3V
• Logic Cells: 1320
• Device System Gates: 16000
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: TQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Total Ram Bits: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-1274

Figure 4. Logic Element
Altera Corporation
Chip-Wide Reset
labctrl1
labctrl2
labctrl3
labctrl4
data1
data2
data3
data4
The programmable flipflop in the LE can be configured for D, T, JK, or SR
operation. The clock and clear control signals on the flipflop can be driven
by global signals, general-purpose I/O pins, or any internal logic. For
combinatorial functions, the flipflop is bypassed and the output of the
LUT drives the outputs of the LE. The LE output can drive both the local
interconnect and the FastTrack Interconnect.
The FLEX 6000 architecture provides two types of dedicated high-speed
data paths that connect adjacent LEs without using local interconnect
paths: carry chains and cascade chains. A carry chain supports high-speed
arithmetic functions such as counters and adders, while a cascade chain
implements wide-input functions such as equivalent comparators with
minimum delay. Carry and cascade chains connect LEs 2 through 10 in an
LAB and all LABs in the same half of the row. Because extensive use of
carry and cascade chains can reduce routing flexibility, these chains
should be limited to speed-critical portions of a design.
Clear/ Preset
Look-Up
Select
Clock
Logic
(LUT)
T
able
Carry-Out
Carry-In
Chain
Carry
FLEX 6000 Programmable Logic Device Family Data Sheet
Cascade-Out
Cascade-In
Cascade
Chain
Register Bypass
D
CLRN
PRN
Q
Programmable
Register
LE-Out
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