EP3C10E144C7N Altera, EP3C10E144C7N Datasheet - Page 4

• Manufacturer Part Number: EP3C10E144C7N
• Description: IC CYCLONE III FPGA 10K 144-EQFP
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C10E144C7N

• Number Of Logic Elements/cells: 10320
• Number Of Labs/clbs: 645
• Total Ram Bits: 423936
• Number Of I /o: 94
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-EQFP
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2425; EP3C10E144C7N

Page 4
Workaround
Table 5. V
3.3-V I/O Power Static Current Issue
Cyclone III Device Family Errata Sheet
Note to
(1) Impedances as listed result in a V
(2) Impedance is over the range of DC to 2.4 MHz.
(3) Minimum capacitors at one each per Cyclone III device to meet the transition current surge. Normal user mode operation likely requires
additional bulk and decoupling capacitors.
Table
EP3C120
CCINT
EP3C25
Device
5:
Supply Impedance and Typical Capacitors
If you use JTAG for initialization, the duration of the current surge is a maximum of
74 TCK clock periods. If you use the CLKUSR pin for initialization, the duration of the
current surge is a maximum of 74 CLKUSR clock periods. Otherwise, the duration of
the current surge is a maximum of 15 s. The fastest rise time within the surge is
150 ns.
To ensure V
to user mode, the system needs to supply the peak transition current.
maximum V
maintaining voltage level stability. Additionally,
with a voltage regulator, that can produce a V
lower than the maximum
Typically a robust V
operation meets the above impedances. For example, the V
Cyclone III FPGA Starter Kit board (3C25) and the Cyclone III FPGA Development Kit
board (3C120) are below the maximum impedances.
Altera has identified an issue with static current in I/O banks powered at 3.3-V V
on Cyclone III EP3C25 Revision B and C and EP3C120 Revision A and B engineering
sample devices. The affected devices might draw more current than expected as
stated in
designing the V
powered at 3.15 V V
Table 6. Additional I/O Current
This issue will be fixed in production silicon for the EP3C25 Revision D and EP3C120
Revision C and their later revisions.
Note to
(1) This current increase per 3.3-V I/O bank is in addition to the existing power estimations shown in the PowerPlay
Early Power Estimator or Quartus II PowerPlay Power Analyzer tools.
EP3C120
Table
EP3C25
Device
CCINT
Table
Maximum V
6;
CCINT
drop of no more than 150 mV.
CCINT
6. You should take the additional I/O current into consideration when
CCIO
voltage level stability during the transition from configuration mode
supply impedance allowed to meet the current surge while
power system on your board. This issue does not affect I/O banks
CCINT
CCIO
CCINT
0.25
0.05
or below.
Maximum Increase of ICCIO Per I/O Banks Powered at 3.3-V V
Supply Impedance
power system designed to handle Cyclone III user mode
CCINT
100 F low ESR tantalum and 10 F ceramic
470 F low ESR tantalum and 100 F
ceramic
Table 5
15 mA
8 mA
supply impedance that is at or
Typical V
lists typical capacitors, along
CCINT
3.3-V I/O Power Static Current Issue
© June 2010 Altera Corporation
CCINT
power systems on the
Capacitor
Table 5
lists the
CCIO
CCIO