EP1C4F400C8N Altera, EP1C4F400C8N Datasheet - Page 54

IC CYCLONE FPGA 4K LE 400-FBGA

EP1C4F400C8N

Manufacturer Part Number
EP1C4F400C8N
Description
IC CYCLONE FPGA 4K LE 400-FBGA
Manufacturer
Altera
Series
Cyclone®r
Datasheet

Specifications of EP1C4F400C8N

Number Of Logic Elements/cells
4000
Number Of Labs/clbs
400
Total Ram Bits
78336
Number Of I /o
301
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
400-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-1806
EP1C4F400C8N

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1C4F400C8N
Manufacturer:
CYCLONE
Quantity:
5 510
Part Number:
EP1C4F400C8N
Manufacturer:
ALTERA
Quantity:
104
Part Number:
EP1C4F400C8N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1C4F400C8N
Manufacturer:
ALTERA
Quantity:
6 000
Part Number:
EP1C4F400C8N
Manufacturer:
ALTERA
Quantity:
1 000
Part Number:
EP1C4F400C8N
Manufacturer:
ALTERA
0
Part Number:
EP1C4F400C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP1C4F400C8N
Quantity:
56
Part Number:
EP1C4F400C8N
0
Company:
Part Number:
EP1C4F400C8N
Quantity:
6 000
Company:
Part Number:
EP1C4F400C8N
Quantity:
3 000
Part Number:
EP1C4F400C8NAA
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1C4F400C8NAB
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1C4F400C8NAC
Manufacturer:
ALTERA
0
Cyclone Device Handbook, Volume 1
2–48
Preliminary
A programmable delay chain on each DQS pin allows for either a 90°
phase shift (for DDR SDRAM), or a 72° phase shift (for FCRAM) which
automatically center-aligns input DQS synchronization signals within the
data window of their corresponding DQ data signals. The phase-shifted
DQS signals drive the global clock network. This global DQS signal clocks
DQ signals on internal LE registers.
These DQS delay elements combine with the PLL’s clocking and phase
shift ability to provide a complete hardware solution for interfacing to
high-speed memory.
The clock phase shift allows the PLL to clock the DQ output enable and
output paths. The designer should use the following guidelines to meet
133 MHz performance for DDR SDRAM and FCRAM interfaces:
Figure 2–34
I/O through the dedicated circuitry to the logic array.
Note to
(1)
EP1C6
EP1C12
EP1C20
Table 2–10. DQ Pin Groups (Part 2 of 2)
Device
The DQS signal must be in the middle of the DQ group it clocks
Resynchronize the incoming data to the logic array clock using
successive LE registers or FIFO buffers
LE registers must be placed in the LAB adjacent to the DQ I/O pin
column it is fed by
EP1C3 devices in the 100-pin TQFP package do not have any DQ pin groups in
I/O bank 1.
Table
illustrates DDR SDRAM and FCRAM interfacing from the
2–10:
144-pin TQFP
240-pin PQFP
256-pin FineLine BGA
240-pin PQFP
256-pin FineLine BGA
324-pin FineLine BGA
324-pin FineLine BGA
400-pin FineLine BGA
Package
Number of × 8 DQ
Pin Groups
4
4
4
4
4
8
8
8
Altera Corporation
Total DQ Pin
Count
32
32
32
32
32
64
64
64
May 2008

Related parts for EP1C4F400C8N