EP1K50TC144-3 Altera, EP1K50TC144-3 Datasheet - Page 59
![IC ACEX 1K FPGA 50K 144-TQFP](/photos/6/70/67061/544-144-tqfp_sml.jpg)
EP1K50TC144-3
Manufacturer Part Number
EP1K50TC144-3
Description
IC ACEX 1K FPGA 50K 144-TQFP
Manufacturer
Altera
Series
ACEX-1K®r
Datasheet
1.EP1K10TC100-3N.pdf
(86 pages)
Specifications of EP1K50TC144-3
Number Of Logic Elements/cells
2880
Number Of Labs/clbs
360
Total Ram Bits
40960
Number Of I /o
102
Number Of Gates
199000
Voltage - Supply
2.375 V ~ 2.625 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
144-TQFP, 144-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
544-1074
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1K50TC144-3
Manufacturer:
ALTERA
Quantity:
7
Company:
Part Number:
EP1K50TC144-3
Manufacturer:
ALTERA
Quantity:
5 510
Company:
Part Number:
EP1K50TC144-3
Manufacturer:
ALTERA
Quantity:
176
Part Number:
EP1K50TC144-3
Manufacturer:
N/A
Quantity:
20 000
Company:
Part Number:
EP1K50TC144-3N
Manufacturer:
ATMEL
Quantity:
5 510
Company:
Part Number:
EP1K50TC144-3N
Manufacturer:
ALTERA42
Quantity:
2 595
Altera Corporation
Notes to tables:
(1)
(2)
(3)
(4)
t
t
t
t
t
t
t
t
t
t
t
t
Table 27. External Reference Timing Parameters
DRR
Table 28. External Timing Parameters
INSU
INH
OUTCO
PCISU
PCIH
PCICO
Table 29. External Bidirectional Timing Parameters
INSUBIDIR
INHBIDIR
OUTCOBIDIR
XZBIDIR
ZXBIDIR
Symbol
Symbol
Symbol
External reference timing parameters are factory-tested, worst-case values specified by Altera. A representative
subset of signal paths is tested to approximate typical device applications.
Contact Altera Applications for test circuit specifications and test conditions.
These timing parameters are sample-tested only.
This parameter is measured with the measurement and test conditions, including load, specified in the PCI Local
Bus Specification, Revision 2.2.
Register-to-register delay via four LEs, three row interconnects, and four local
interconnects
Setup time with global clock at IOE register
Hold time with global clock at IOE register
Clock-to-output delay with global clock at IOE register
Setup time with global clock for registers used in PCI designs
Hold time with global clock for registers used in PCI designs
Clock-to-output delay with global clock for registers used in PCI designs
Setup time for bidirectional pins with global clock at same-row or same-
column LE register
Hold time for bidirectional pins with global clock at same-row or same-column
LE register
Clock-to-output delay for bidirectional pins with global clock at IOE register
Synchronous IOE output buffer disable delay
Synchronous IOE output buffer enable delay, slow slew rate = off
Tables 27
and their symbols.
through
Parameter
Parameter
Parameter
29
ACEX 1K Programmable Logic Device Family Data Sheet
describe the ACEX 1K external timing parameters
Note (1)
Note (3)
(2)
(3)
(3)
(3)
(3),
(3),
(3),
CI = 35 pF
CI = 35 pF
CI = 35 pF
Conditions
Conditions
Conditions
(4)
(4)
(4)
59
13