EP2C35F672C8 Altera, EP2C35F672C8 Datasheet - Page 136
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EP2C35F672C8
Manufacturer Part Number
EP2C35F672C8
Description
IC CYCLONE II FPGA 33K 672-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet
1.EP2C5T144C8N.pdf
(168 pages)
Specifications of EP2C35F672C8
Number Of Logic Elements/cells
33216
Number Of Labs/clbs
2076
Total Ram Bits
483840
Number Of I /o
475
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
33216
# I/os (max)
475
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
33216
Ram Bits
483840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FBGA
For Use With
NANO-CYCLONE - KIT NANOBOARD AND CYCLONEII DC807-1002 - DAUGHTER CARD ALTERA CYCLONE IIP0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1089
EP2C35F672C8ES
EP2C35F672C8ES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2C35F672C8
Manufacturer:
ALTERA
Quantity:
20 000
Company:
Part Number:
EP2C35F672C8N
Manufacturer:
YAGEO
Quantity:
500 000
Company:
Part Number:
EP2C35F672C8N
Manufacturer:
ALTERA
Quantity:
500
Part Number:
EP2C35F672C8N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Timing Specifications
5–46
Cyclone II Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
LVDS
RSDS
MINI_LVDS
PCI
PCI-X
Table 5–43. Cyclone II I/O Output Delay for Row Pins (Part 4 of 4)
I/O Standard
This is the default setting in the Quartus II software.
These numbers are for commercial devices.
These numbers are for automotive devices.
Table
5–43:
Strength
Drive
—
—
—
—
—
Maximum Input and Output Clock Rate
Maximum clock toggle rate is defined as the maximum frequency
achievable for a clock type signal at an I/O pin. The I/O pin can be a
regular I/O pin or a dedicated clock I/O pin.
The maximum clock toggle rate is different from the maximum data bit
rate. If the maximum clock toggle rate on a regular I/O pin is 300 MHz,
the maximum data bit rate for dual data rate (DDR) could be potentially
as high as 600 Mbps on the same I/O pin.
Table 5–44
specifies the maximum output clock toggle rates at default load.
Table 5–46
for non-default load.
To calculate the output toggle rate for a non-default load, use this
formula:
t
t
t
t
t
t
t
t
t
t
Parameter
O P
D I P
O P
D I P
O P
D I P
O P
D I P
O P
D I P
The toggle rate for a non-default load
specifies the maximum input clock toggle rates.
specifies the derating factors for the output clock toggle rate
Industrial
motive
/Auto-
1216
1340
1216
1340
1216
1340
1113
1113
989
989
Fast Corner
Commer-
1275
1407
1275
1407
1275
1407
1036
1168
1036
1168
cial
Speed
Grade
2089
2297
2089
2297
2089
2297
2070
2278
2070
2278
–6
Speed
Grade
2184
2421
2184
2421
2184
2421
2214
2451
2214
2451
(2)
–7
Speed
Grade
2272
2545
2272
2545
2272
2545
2352
2625
2352
2625
(3)
–7
Altera Corporation
February 2008
Table 5–45
Speed
Grade
2278
2545
2278
2545
2278
2545
2358
2625
2358
2625
–8
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps