EP2C35F672C8 Altera, EP2C35F672C8 Datasheet - Page 19

IC CYCLONE II FPGA 33K 672-FBGA

EP2C35F672C8

Manufacturer Part Number
EP2C35F672C8
Description
IC CYCLONE II FPGA 33K 672-FBGA
Manufacturer
Altera
Series
Cyclone® IIr
Datasheet

Specifications of EP2C35F672C8

Number Of Logic Elements/cells
33216
Number Of Labs/clbs
2076
Total Ram Bits
483840
Number Of I /o
475
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Family Name
Cyclone® II
Number Of Logic Blocks/elements
33216
# I/os (max)
475
Frequency (max)
402.58MHz
Process Technology
90nm
Operating Supply Voltage (typ)
1.2V
Logic Cells
33216
Ram Bits
483840
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
672
Package Type
FBGA
For Use With
NANO-CYCLONE - KIT NANOBOARD AND CYCLONEII DC807-1002 - DAUGHTER CARD ALTERA CYCLONE IIP0301 - DE2 CALL FOR ACADEMIC PRICING544-1733 - PCI KIT W/CYCLONE II EP2C35N
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1089
EP2C35F672C8ES

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Logic Array
Blocks
Figure 2–5. Cyclone II LAB Structure
Altera Corporation
February 2007
Direct link
interconnect
from adjacent
block
Direct link
interconnect
to adjacent
block
Each LAB consists of the following:
The local interconnect transfers signals between LEs in the same LAB.
Register chain connections transfer the output of one LE’s register to the
adjacent LE’s register within an LAB. The Quartus II Compiler places
associated logic within an LAB or adjacent LABs, allowing the use of
local, and register chain connections for performance and area efficiency.
Figure 2–5
16 LEs
LAB control signals
LE carry chains
Register chains
Local interconnect
LAB
shows the Cyclone II LAB.
Local Interconnect
Cyclone II Device Handbook, Volume 1
Row Interconnect
Cyclone II Architecture
Direct link
interconnect
from adjacent
block
Direct link
interconnect
to adjacent
block
Column
Interconnect
2–7

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