EP2S60F484C5N Altera, EP2S60F484C5N Datasheet - Page 202
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EP2S60F484C5N
Manufacturer Part Number
EP2S60F484C5N
Description
IC STRATIX II FPGA 60K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F484C5N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
334
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
60440
# I/os (max)
334
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1908
EP2S60F484C5N
EP2S60F484C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F484C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S60F484C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Timing Model
5–66
Stratix II Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
1.8-V HSTL
Class I
1.5-V HSTL
Class I
LVDS
HyperTransport
Table 5–76. Stratix II I/O Output Delay for Row Pins (Part 3 of 3)
I/O Standard
This is the default setting in the Quartus II software.
These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
Table
5–76:
4 mA
6 mA
8 mA
10 mA
12 mA
(1)
4 mA
6 mA
8 mA
Strength
Drive
(1)
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Parameter
O P
D I P
O P
D I P
O P
D I P
O P
D I P
O P
D I P
O P
D I P
O P
D I P
O P
D I P
O P
D I P
O P
D I P
Maximum Input & Output Clock Toggle Rate
Maximum clock toggle rate is defined as the maximum frequency
achievable for a clock type signal at an I/O pin. The I/O pin can be a
regular I/O pin or a dedicated clock I/O pin.
Industrial
1018
1005
972
930
975
933
958
916
962
920
953
911
970
928
974
932
960
918
976
963
Minimum Timing
Commercial
1019
1022
1004
1008
1018
1021
1006
1067
1024
1053
1010
976
979
961
965
999
956
975
978
963
Speed
Grade
1610
1555
1580
1525
1576
1521
1567
1512
1566
1511
1591
1536
1579
1524
1572
1517
1723
1668
1723
1668
(2)
-3
Speed
Grade
1689
1632
1658
1601
1653
1596
1644
1587
1643
1586
1669
1612
1657
1600
1649
1592
1808
1751
1808
1751
(3)
-3
Speed
Grade
1850
1787
1816
1753
1811
1748
1801
1738
1800
1737
1828
1765
1815
1752
1807
1744
1980
1917
1980
1917
-4
Altera Corporation
Speed
Grade
1956
1883
1920
1847
1916
1843
1905
1832
1904
1831
1933
1860
1919
1846
1911
1838
2089
2016
2089
2016
-5
April 2011
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps