EP2S60F484C5N Altera, EP2S60F484C5N Datasheet - Page 207
![IC STRATIX II FPGA 60K 484-FBGA](/photos/6/72/67258/544-484-fbga_sml.jpg)
EP2S60F484C5N
Manufacturer Part Number
EP2S60F484C5N
Description
IC STRATIX II FPGA 60K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F484C5N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
334
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
60440
# I/os (max)
334
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1908
EP2S60F484C5N
EP2S60F484C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F484C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S60F484C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
April 2011
Differential
SSTL-18 Class I
(3)
Differential
SSTL-18 Class II
(3)
1.8-V Differential
HSTL Class I
1.8-V Differential
HSTL Class II
1.5-V Differential
HSTL Class I
1.5-V Differential
HSTL Class II
3.3-V PCI
3.3-V PCI-X
LVDS
HyperTransport
technology (4),
LVPECL
3.3-V LVTTL
2.5-V LVTTL
Table 5–78. Maximum Output Toggle Rate on Stratix II Devices (Part 3 of 5)
I/O Standard
(6)
(5)
(3)
(3)
(3)
(3)
(6)
OCT 50 Ω
OCT 50 Ω
Strength
10 mA
12 mA
16 mA
18 mA
20 mA
10 mA
12 mA
16 mA
18 mA
20 mA
10 mA
12 mA
16 mA
18 mA
20 mA
Drive
4 mA
6 mA
8 mA
8 mA
4 mA
6 mA
8 mA
4 mA
6 mA
8 mA
1,000
1,000
Column I/O Pins (MHz)
200
350
450
500
700
200
400
450
550
300
500
650
700
700
500
550
650
350
500
700
700
700
600
650
700
400
350
-3
-
-
150
250
300
400
550
200
350
400
500
300
450
600
650
700
500
500
550
300
500
650
700
700
600
600
650
790
790
400
350
-4
-
-
150
200
300
400
400
150
350
400
450
300
450
600
600
650
450
500
550
300
450
600
650
700
550
600
600
670
670
350
300
-5
-
-
200
350
450
500
350
500
500
400
350
Row I/O Pins (MHz)
-3
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Stratix II Device Handbook, Volume 1
150
250
300
400
350
500
500
400
350
-4
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DC & Switching Characteristics
150
200
300
400
297
500
500
350
300
-5
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Note (1)
1,000
1,000
Clock Outputs (MHz)
200
350
450
500
650
200
400
450
550
300
500
650
700
700
500
550
550
350
500
700
700
700
600
650
700
450
450
400
350
-3
-
150
250
300
400
550
200
350
400
500
300
450
600
650
700
500
500
550
300
500
650
700
700
600
600
650
790
790
400
400
400
350
-4
-
150
200
300
400
400
150
350
400
450
300
450
600
600
650
450
500
550
300
450
600
650
700
550
600
600
670
670
300
300
350
300
-5
5–71
-