EP2S60F484C5N Altera, EP2S60F484C5N Datasheet - Page 221
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EP2S60F484C5N
Manufacturer Part Number
EP2S60F484C5N
Description
IC STRATIX II FPGA 60K 484-FBGA
Manufacturer
Altera
Series
Stratix® IIr
Datasheet
1.EP2S15F484I4N.pdf
(238 pages)
Specifications of EP2S60F484C5N
Number Of Logic Elements/cells
60440
Number Of Labs/clbs
3022
Total Ram Bits
2544192
Number Of I /o
334
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
484-FBGA
Family Name
Stratix II
Number Of Logic Blocks/elements
60440
# I/os (max)
334
Frequency (max)
609.76MHz
Process Technology
90nm (CMOS)
Operating Supply Voltage (typ)
1.2V
Logic Cells
60440
Ram Bits
2544192
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
484
Package Type
FC-FBGA
For Use With
544-1700 - DSP KIT W/STRATIX II EP2S60N544-1697 - NIOS II KIT W/STRATIX II EP2S60N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1908
EP2S60F484C5N
EP2S60F484C5N
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2S60F484C5N
Manufacturer:
ALTERA
Quantity:
238
Part Number:
EP2S60F484C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Altera Corporation
April 2011
Notes to
(1)
(2)
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL
LVPECL
Table 5–85. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 & -5
Devices (Part 2 of 2)
DDIO Column Output I/O
Table 5–85
The DCD specification is based on a no logic array noise condition.
Table
Standard
5–85:
assumes the input clock has zero DCD.
Notes
3.3-V LVTTL
3.3-V LVCMOS
2.5V
1.8V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
Table 5–86. Maximum DCD for DDIO Output on Row I/O Pins with PLL in the
Clock Path (Part 1 of 2)
Row DDIO Output I/O
(1),
Maximum DCD Based on I/O Standard of Input Feeding the DDIO
3.3/2.5 V
(2)
Standard
335
320
330
330
330
330
420
180
TTL/CMOS
Clock Port (No PLL in the Clock Path)
1.8/1.5 V
385
385
390
360
470
180
390
375
Maximum DCD (PLL Output Clock Feeding
Note (1)
-3 Device
110
105
65
75
85
65
60
50
50
55
Stratix II Device Handbook, Volume 1
DDIO Clock Port)
SSTL-2
2.5 V
180
155
65
70
60
60
60
90
DC & Switching Characteristics
-4 & -5 Device
SSTL/HSTL
1.8/1.5 V
100
100
105
100
165
180
75
90
75
70
65
70
70
65
80
70
70
70
Unit
ps
ps
ps
ps
ps
ps
ps
ps
Unit
5–85
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps