EP3SL150F780C4N Altera, EP3SL150F780C4N Datasheet - Page 256

• Manufacturer Part Number: EP3SL150F780C4N
• Description: IC STRATIX III FPGA 150K 780FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F780C4N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 488
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 780-FBGA
• Family Name: Stratix III
• Number Of Logic Blocks/elements: 142500
• # I/os (max): 488
• Frequency (max): 450MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.1V
• Logic Cells: 142500
• Ram Bits: 6543360
• Operating Supply Voltage (min): 1.05V
• Operating Supply Voltage (max): 1.15V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2403; EP3SL150F780C4NES

8–8
Figure 8–3. Number of DQS/DQ Groups per Bank in EP3SE50, EP3SL50, and EP3SL70 Devices in the 484-pin FineLine BGA
Package
Notes to
(1) This device does not support ×32/×36 mode.
(2) You can also use DQS/DQSn pins in some of the ×4 groups as RUP/RDN pins. You cannot use a ×4 group for memory interfaces if two pins of
(3) Some of the DQS/DQ pins in this bank can also be used as configuration pins. Choose the DQS/DQ pins that are not going to be used by your
(4) All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, and CLK10n)
Stratix III Device Handbook, Volume 1
the group are being used as RUP and RDN pins for OCT calibration. You can still use the ×16/×18 or ×32/×36 groups that includes these ×4 groups.
However, there are restrictions on using ×8/×9 groups that include these ×4 groups as described on
configuration scheme.
Figure
(Note 1)
8–3:
26 User I/Os (4)
26 User I/Os (4)
I/O Bank 1A (2)
I/O Bank 1C (3)
I/O Bank 2A (2)
24 User I/Os
24 User I/Os
I/O Bank 2C
x16/x18=0
x16/x18=0
x16/x18=0
x16/x18=0
x8/x9=1
x8/x9=1
x8/x9=1
x8/x9=1
DLL 1
DLL 0
x4=3
x4=3
x4=3
4=3
EP3SE50, EP3SL50, and EP3SL70 Devices
24 User I/Os
24 User I/Os
I/O Bank 8C
I/O Bank 3C
x16/x18=0
x16/x18=0
x8/x9=1
x8/x9=1
x4=2
x4=2
484-pin FineLine BGA
24 User I/Os
24 User I/Os
I/O Bank 4C
I/O Bank 7C
x16/x18=0
x16/x18=0
x8/x9=1
x8/x9=1
x4=3
x4=3
Chapter 8: External Memory Interfaces in Stratix III Devices
I/O Bank 6A (2)
26 User I/Os (4)
26 User I/Os (4)
I/O Bank 5A (2)
24 User I/Os
24 User I/Os
I/O Bank 6C
I/O Bank 5C
x16/x18=0
x16/x18=0
x16/x18=0
x16/x18=0
x8/x9=1
x8/x9=1
page
x8/x9=1
x8/x9=1
DLL 3
DLL 2
x4=3
x4=3
x4=3
x4=3
8–5.
© March 2010 Altera Corporation
Memory Interfaces Pin Support