EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 174

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

1–174
Table 1–89. EP3SL200 Column Pin Delay Adders for Regional Clock
Table 1–90. EP3SL200 Row Pin Delay Adders for Regional Clock
Table 1–91. EP3SL340 Column Pins Input Timing Parameters (Part 1 of 4)
Stratix III Device Handbook, Volume 2
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
RCLK input adder
RCLK PLL input adder
RCLK output adder
RCLK PLL output adder
3.3-V LVTTL
3.3-V
LVCMOS
Standard
I/O
Parameter
Parameter
GCLK
GCLK
GCLK
GCLK
Clock
PLL
PLL
Table 1–89
must be added to the GCLK values. Use these adder values to determine I/O timing
when the I/O pin is driven using the regional clock. This applies to all I/O standards
supported by Stratix III devices.
Table 1–89
Table 1–90
EP3SL340 I/O Timing Parameters
Table 1–91
devices for single-ended I/O standards.
Table 1–91
I/O standards.
t
t
t
t
t
t
t
t
su
su
su
su
h
h
h
h
Industrial
Industrial
-0.211
-0.278
0.204
0.036
1.904
0.272
-0.15
0.14
Industrial
-1.345
-1.691
-1.345
-1.691
1.486
1.996
1.486
1.996
Fast Model
Fast Model
Fast Model
and
lists the EP3SL200 column pin delay adders when using the regional clock.
lists the EP3SL200 row pin delay adders when using the regional clock.
through
lists the EP3SL340 column pins input timing parameters for single-ended
Commercial
Commercial
-0.234
-0.306
0.235
0.046
1.965
Table 1–90
Commercial
0.301
0.149
-0.15
-1.335
-1.691
-1.335
-1.691
1.476
1.996
1.476
1.996
Table 1–94
-0.332
0.378
0.078
3.193
-0.418 -0.434 -0.486 -0.472 -0.592 -0.464 -0.493 -0.472 -0.592
-0.227 -0.233 -0.254 -0.243 -0.322 -0.243 -0.258 -0.243 -0.322
1.1 V
V
0.446
0.226
1.1 V
V
list the EP3SL200 regional clock (RCLK) adder values that
C2
-2.017 -2.061 -2.330 -2.245 -2.542 -2.061 -2.330 -2.245 -2.542
-2.554 -2.585 -2.890 -2.799 -3.373 -2.585 -2.890 -2.799 -3.373
-2.017 -2.061 -2.330 -2.245 -2.542 -2.061 -2.330 -2.245 -2.542
-2.554 -2.585 -2.890 -2.799 -3.373 -2.585 -2.890 -2.799 -3.373
CCL
C2
CCL
2.232
3.031
2.232
3.031
1.1 V
V
C2
=
CCL
=
list the maximum I/O timing parameters for EP3SL340
=
Chapter 1: Stratix III Device Datasheet: DC and Switching Characteristics
-0.328
0.378
0.078
3.323
0.424
0.216
1.1 V
1.1 V
V
V
2.284
3.081
2.284
3.081
C3
C3
CCL
CCL
1.1 V
V
C3
CCL
=
=
=
-0.047 -0.038 -0.036
0.403
3.688
0.473
0.235
-0.34
1.1 V
1.1 V
V
V
2.574
3.434
2.574
3.434
C4
C4
CCL
CCL
1.1 V
V
C4
CCL
=
=
=
-0.334 -0.464 -0.327 -0.339 -0.334 -0.464
0.392
3.496
0.226
1.1 V
V
1.1 V
V
0.46
2.476
3.313
2.476
3.313
1.1 V
CCL
CCL
V
CCL
=
=
=
C4L
C4L
C4L
0.509
3.804
0.9 V
0.547
0.306
V
0.9 V
V
2.783
3.912
2.783
3.912
0.9 V
CCL
V
CCL
CCL
=
=
=
© July 2010 Altera Corporation
0.387
0.085
3.351
1.1 V
V
0.454
0.232
1.1 V
V
2.284
3.081
2.284
3.081
1.1 V
V
I3
CCL
I3
CCL
I3
CCL
=
=
=
-0.046 -0.038 -0.036
0.411
3.716
1.1 V
V
0.481
0.254
2.574
3.434
2.574
3.434
1.1 V
V
1.1 V
V
I4
CCL
I4
CCL
I4
CCL
=
=
=
I/O Timing
0.392
3.496
1.1 V
V
2.476
3.313
2.476
3.313
0.226
1.1 V
1.1 V
V
V
0.46
CCL
CCL
CCL
=
=
=
I4L
I4L
I4L
0.509
3.804
0.9 V
2.783
3.912
2.783
3.912
V
0.9 V
0.547
0.306
V
0.9 V
V
CCL
CCL
CCL
=
=
=
Units
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns