EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet

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... Innovation Drive San Jose, CA 95134 www.altera.com Stratix III Device Handbook, Software Version: Document Version: Document Date: Volume 1 10.0 2.2 © March 2011 ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation ...

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... Chapter Revision Dates Additional Information How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-xxv Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-xxv Chapter I. Device Core Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-1 Chapter 1. Stratix III Device Family Overview Features Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Architecture Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 Logic Array Blocks and Adaptive Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 MultiTrack Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 TriMatrix Embedded Memory Blocks ...

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... True Dual-Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 Shift-Register Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 ROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 FIFO Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 Clocking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Independent Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Input/Output Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-19 Read/Write Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 Single Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-20 Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation ...

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... Rounding and Saturation Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31 DSP Block Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34 Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 FIR Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35 FFT Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-40 Software Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-42 Chapter 6. Clock Networks and PLLs in Stratix III Devices © March 2011 Altera Corporation v Stratix III Device Handbook, Volume 1 ...

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... Dynamic Phase-Shifting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49 PLL Cascading and Clock Network Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52 Spread-Spectrum Tracking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52 PLL Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-52 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53 Chapter II. I/O Interfaces Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . II-1 Chapter 7. Stratix III Device I/O Features Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation ...

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... Differential I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40 I/O Banks Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40 Non-Voltage-Referenced Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-40 Voltage-Referenced Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-41 Mixing Voltage-Referenced and Non-Voltage-Referenced Standards . . . . . . . . . . . . . . . . . . . . . 7-41 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42 Chapter 8. External Memory Interfaces in Stratix III Devices © March 2011 Altera Corporation ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-26 D vii Stratix III Device Handbook, Volume 1 ...

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... Differential I/O Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-12 Left/Right PLLs (PLL_Lx/ PLL_Rx 9-12 Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-14 Source-Synchronous Timing Budget . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 Differential Data Orientation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 Differential I/O Bit Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-15 Receiver Skew Margin for Non-DPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-17 Stratix III Device Handbook, Volume 9-11 © March 2011 Altera Corporation ...

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... PS Configuration Using a MAX II Device as an External Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-27 PS Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-32 PS Configuration Using a Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 PS Configuration Using a Download Cable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-33 JTAG Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-37 Jam STAPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-43 Device Configuration Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-43 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-51 © March 2011 Altera Corporation ix Stratix III Device Handbook, Volume 1 ...

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... Stratix III Design Security Solution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-3 Security Modes Available . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 Volatile Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 Non-Volatile Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 Non-Volatile Key with Tamper Protection Bit Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4 No Key Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 Supported Configuration Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-5 Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation ...

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... External Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 Chapter VI. Packaging Information Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VI-1 Chapter 17. Stratix III Device Packaging Information Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 © March 2011 Altera Corporation xi Stratix III Device Handbook, Volume 1 ...

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... Stratix III Device Handbook, Volume 1 © March 2011 Altera Corporation ...

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... Part Number: SIII51009-1.9 Chapter 10 Hot Socketing and Power-On Reset in Stratix III Devices Revised: Part Number: SIII51010-1.7 Chapter 11 Configuring Stratix III Devices Revised: Part Number: SIII51011-2.0 © March 2011 Altera Corporation March 2010 February 2009 October 2008 May 2009 March 2010 July 2010 ...

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... Chapter 16 Programmable Power and Temperature-Sensing Diodes in Stratix III Devices Revised: Part Number: SIII51016-1.5 Chapter 17 Stratix III Device Packaging Information Revised: Part Number: SIII51017-1.7 Stratix III Device Handbook, Volume 1 March 2010 July 2010 May 2009 March 2010 February 2009 March 2010 © March 2011 Altera Corporation ...

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... Figure 4–15: Stratix III True Dual-Port Memory Figure 4–16: Stratix III True Dual-Port Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 Figure 4–17: Stratix III Shift-Register Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18 Figure 4–18: Stratix III Read-During-Write Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21 © March 2011 Altera Corporation (Note 2-9 (Note 2-11 (Note 1) ...

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... Figure 6–20: External Clock Outputs for Top/Bottom PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22 Figure 6–21: External Clock Outputs for Left/Right PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23 Figure 6–22: Stratix III PLL Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 Stratix III Device Handbook, Volume 1 (Note 4-22 (Note 4-22 (Note 4-23 (Note 1) © March 2011 Altera Corporation List of Figures . . . . . . . 6-4 ...

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... Figure 7–20: SSTL I/O Standard Termination for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-33 Figure 7–21: HSTL I/O Standard Termination for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-34 Figure 7–22: Differential SSTL I/O Standard Termination for Stratix III Devices . . . . . . . . . . . . . . . . . . . 7-35 © March 2011 Altera Corporation (Note 1), (2), (3), (4), (5), (6), (7), (8), (2) ...

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... List of Figures . . . . . . . . . . . . . . . . . . . . . 7-36 ( 7-38 1 8-3 (Note 8-38 © March 2011 Altera Corporation ...

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... Figure 12–5: Remote System Upgrade Circuit Data Path Figure 12–6: Remote System Upgrade Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-9 Figure 12–7: Remote System Upgrade Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-10 Figure 12–8: Interface Signals Between the ALTREMOTE_UPDATE Megafunction and the Nios II Proces- © March 2011 Altera Corporation (Note 9-16 (Note ...

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... Figure 15–2: Enabling the Error Detection CRC Feature in the Quartus II Software . . . . . . . . . . . . . . . . 15-11 Figure 16–1: Stratix III Power Management Example Figure 16–2: TEMPDIODEP and TEMPDIODEN External Pin Connections . . . . . . . . . . . . . . . . . . . . . . . 16-6 Figure 16–3: TSD Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6 Stratix III Device Handbook, Volume 14-4 (Note 1), ( 16-5 List of Figures © March 2011 Altera Corporation ...

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... Table 6–12: PLL Input Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24 Table 6–13: PLL Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-25 Table 6–14: Clock Feedback Mode Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-26 Table 6–15: Real-Time PLL Reconfiguration Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-44 Table 6–16: Top/Bottom PLL Reprogramming Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-46 © March 2011 Altera Corporation (Note 1-4 (Note 5-31 (Note 1) ...

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... Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5 RAMP List of Tables . . . . . . . . . . . . . . . . . . . 7-3 (Note 1), (2) . 8-25 1), (2), ( 9-3 (Note 1), ( © March 2011 Altera Corporation ...

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... Table 16–2: Stratix III Power Supply Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-4 Table 16–3: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-7 Table 17–1: FineLine and Hybrid FineLine BGA Packages for Stratix III Devices . . . . . . . . . . . . . . . . . . . 17-1 Table 17–2: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17-2 © March 2011 Altera Corporation (Note 11-14 (Note 1) ...

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... Stratix III Device Handbook, Volume 1 List of Tables © March 2011 Altera Corporation ...

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... Technical training Product literature Non-technical support (General) (Software Licensing) Note: (1) You can also contact your local Altera sales office or sales representative. Typographic Conventions The following table shows the typographic conventions that this document uses. Visual Cue Bold Type with Initial Capital ...

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... A warning calls attention to a condition or possible situation that can cause injury to the user. The angled arrow indicates you should press the Enter key. The feet direct you to more information on a particular topic. Typographic Conventions , , data1 tdi , e.g resetn . Also, sections of an actual ) are shown in Courier. TRI © March 2011 Altera Corporation ...

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... Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook. © July 2010 Altera Corporation Section I. Device Core III ® Stratix III Device Handbook, Volume 1 ...

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... I–2 Stratix III Device Handbook, Volume 1 Section I: Device Core Revision History © July 2010 Altera Corporation ...

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... III family provides one of the most architecturally advanced, ® high-performance, low-power FPGAs in the marketplace. Stratix III FPGAs lower power consumption through Altera’s innovative Programmable Power Technology, which provides the ability to turn on the performance where needed and turn down the power consumption for blocks not in use. Selectable Core Voltage and the latest in silicon process optimizations are also employed to deliver the industry’ ...

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... M144K TriMatrix memory blocks Nios II embedded processor support ■ ® ■ Support for multiple intellectual property megafunctions from Altera functions and Altera Megafunction Partners Program (AMPP Stratix III Device Handbook, Volume 1 Chapter 1: Stratix III Device Family Overview Features Summary MegaCore ® ...

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... Stratix III devices are available in space-saving FineLine BGA (FBGA) packages (refer to Table 1–2 and © March 2010 Altera Corporation Total M9K M144K MLAB Embedded Blocks ...

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... FineLine BGA FineLine BGA (3) (3) — — — — — — — — 976 — 976 1,120 — — — — — — 976 — II ® 1517 Pin 1760 Pin 1.00 1.00 1,600 1,849 40/40 43/43 © March 2010 Altera Corporation ...

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... Commercial –4L EP3SE50 Industrial –3, –4, –4L Commercial — EP3SE80 Industrial — Commercial — EP3SE110 Industrial — © March 2010 Altera Corporation Dimension 780-Pin 780-Pin 1152-Pin Hybrid FineLine FineLine FineLine BGA BGA BGA –2, –3,–4, — — –4L – ...

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... Chapter 1: Stratix III Device Family Overview Architecture Features 1152-Pin 1760-Pin 1517-Pin Hybrid FineLine FineLine FineLine BGA BGA BGA –2, –3, –4, — — –4L — –3, –4,–4L — Logic Array Blocks and chapter. © March 2010 Altera Corporation ...

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... DSP blocks to implement finite impulse response (FIR) filters, complex FIR filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, and discrete cosine transform (DCT) functions. © March 2010 Altera Corporation MultiTrack Interconnect in Stratix III Devices TriMatrix Embedded Memory Blocks in Stratix III Devices Stratix III Device Handbook, Volume 1 1– ...

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... Stratix III PLLs also support external feedback mode, spread-spectrum input clock tracking, and post-scale counter cascading. Stratix III Device Handbook, Volume 1 Chapter 1: Stratix III Device Family Overview DSP Blocks in Stratix III Devices chapter. © March 2010 Altera Corporation Architecture Features ...

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... SFI-4, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSI. Stratix III devices support 2×, 4×, 6×, 7×, 8×, and 10× SERDES modes for high-speed differential I/O interfaces and © March 2010 Altera Corporation Clock Networks and PLLs in Stratix III Devices ) termination with auto calibration for single-ended I/O standards ...

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... All configuration schemes use either an external controller (for example, a MAX device or microprocessor), a configuration device download cable. Stratix III Device Handbook, Volume 1 High Speed Differential I/O Interfaces with DPA in chapter. Hot Socketing and Power-On Reset in Stratix III Chapter 1: Stratix III Device Family Overview Architecture Features II ® © March 2010 Altera Corporation ...

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... Advanced Encryption Standard (AES) algorithm, an industry standard encryption algorithm that is FIPS-197 certified and requires a 256-bit security key. © March 2010 Altera Corporation Configuring Stratix III Devices Remote System Upgrades with Stratix III Devices IEEE 1149.1 (JTAG) Boundary Scan Testing in chapter. 1– ...

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... Programmable Power and Temperature Sensing Diode in Stratix III Devices ■ AN 437: Power Optimization in Stratix III FPGAs Stratix III Programmable Power White Paper ■ Stratix III Device Handbook, Volume 1 chapter. chapter. Chapter 1: Stratix III Device Family Overview Architecture Features Design Security in SEU chapter © March 2010 Altera Corporation ...

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... The following section describes Stratix III device software support and ordering information. Software Support Stratix III devices are supported by the Altera Quartus II design software, version 6.1 and later, which provides a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus II software includes HDL and schematic design entry, compilation and logic synthesis, full simulation and ...

Page 42

... Chapter 1: Stratix III Device Family Overview Chapter Revision History Stratix III Device Package Optional Suffix Indicates specific device options ES: Engineering sample N: Lead-free devices L: Low-voltage devices Speed Grade with 2 being the fastest Operating Temperature = Commercial temperature ( Industrial temperature ( 100 C) J © March 2010 Altera Corporation ...

Page 43

... Minor formatting changes, fixed PLL numbers and ALM, LE and MLAB bit counts in May 2007 1.1 Table 1–1. November 2006 1.0 Initial Release. © March 2010 Altera Corporation Changes Made Updated “Introduction”. Updated Table 1–1. Updated Table 1–2. Added Table 1–5. Updated “Reference and Ordering Information”. ...

Page 44

... Stratix III Device Handbook, Volume 1 Chapter 1: Stratix III Device Family Overview Chapter Revision History © March 2010 Altera Corporation ...

Page 45

... LAB interconnects. © February 2009 Altera Corporation 2. Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices II Compiler places associated logic in an LAB or adjacent LABs, ® ...

Page 46

... Figure 2–2 shows an overview of LAB and MLAB TriMatrix Embedded Memory Blocks in Stratix III Logic Array Blocks ALMs Direct link interconnect from adjacent block Direct link interconnect to adjacent block Column Interconnects of Variable Speed & Length Figure 2–2. The © February 2009 Altera Corporation ...

Page 47

... LAB's local interconnect through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each ALM can drive 30 ALMs through fast local and direct link interconnects. © February 2009 Altera Corporation (1) ALM (1) ...

Page 48

... LAB interconnect's inherent low skew allows clock and control TM Figure 2–4shows the LAB control signal Logic Array Blocks Direct link interconnect from right LAB, TriMatrix memory block, DSP block, or IOE output ALMs Direct link interconnect to right © February 2009 Altera Corporation ...

Page 49

... Each ALM drives all types of interconnects: local, row, column, carry chain, shared arithmetic chain, register chain, and direct link interconnects. the Stratix III ALM while ALM. © February 2009 Altera Corporation There are two unique clock signals per LAB. labclk0 labclk1 ...

Page 50

... Stratix III Device Handbook, Volume 1 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices carry_in reg_chain_in labclk adder0 adder1 reg_chain_out carry_out Adaptive Logic Modules To general or local routing To general local routing reg0 To general local routing reg1 To general or local routing © February 2009 Altera Corporation ...

Page 51

... Either general-purpose I/O pins or internal logic can drive the clock enable. For combinational functions, the register is bypassed and the output of the LUT drives directly to the outputs of an ALM. © February 2009 Altera Corporation 2–7 Stratix III Device Handbook, Volume 1 ...

Page 52

... LUT combinations in normal mode. Stratix III Device Handbook, Volume 1 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices for more information on the LAB-wide © February 2009 Altera Corporation Adaptive Logic Modules Figure 2–7 ...

Page 53

... For the packing of 2 five-input functions into one ALM, the functions must have at least two common inputs. The common inputs are dataa and datab. The combination of a four-input function with a five-input function requires one common input (either dataa or datab). © February 2009 Altera Corporation dataf0 datae0 combout0 ...

Page 54

... Six-Input out0 dataa LUT datab (Function0) datac datad out1 Six-Input LUT (Function1) datae1 dataf1 Figure 2–9). If datae1 and dataf1 are utilized, the output drives to Adaptive Logic Modules 2–8. The shared inputs are combout0 combout1 © February 2009 Altera Corporation ...

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... The ALM in arithmetic mode uses two sets of 2 four-input LUTs along with two dedicated full adders. The dedicated adders allow the LUTs to be available to perform pre-adder logic; therefore, each adder can add the output of 2 four-input functions. © February 2009 Altera Corporation (Note 1) 6-Input LUT ...

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... Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices carry_in adder0 4-Input LUT D reg0 4-Input LUT adder1 4-Input LUT D 4-Input reg1 LUT carry_out Adaptive Logic Modules Figure 2–11, the To general or local routing To general or Q local routing To general or local routing To general or Q local routing © February 2009 Altera Corporation ...

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... LAB-wide signals that affect all registers in the LAB. These signals can also be individually disabled or enabled per register. The Quartus II software automatically places any registers that are not used by the counter into other LABs. © February 2009 Altera Corporation Adder output is not used. Comb & ...

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... Figure 2–13 Stratix III Device Handbook, Volume 1 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices shows the ALM using this feature. Adaptive Logic Modules “ALM Interconnects” on © February 2009 Altera Corporation ...

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... An example of a three-bit add operation utilizing the shared arithmetic mode is shown in Figure obtained using the LUTs, while the result (R[3..0]) is computed using the dedicated adders. © February 2009 Altera Corporation shared_arith_in carry_in labclk 4-Input LUT ...

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... Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices ALM Implementation ALM 1 3-Input LUT X0 3-Input Y0 LUT Z0 X1 3-Input Y1 LUT Z1 3-Input LUT ALM 2 3-Input LUT X2 3-Input Y2 LUT Z2 X3 3-Input Y3 LUT Z3 3-Input LUT © February 2009 Altera Corporation Adaptive Logic Modules shared_arith_in = '0' carry_in = ' ...

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... ALM. mode. Figure 2–15. LUT Register from Two Combinational Blocks clk aclr datain(datac) sclr © February 2009 Altera Corporation for more information on shared Figure 2–15 shows the register constructed using two Figure 2–16 shows the ALM in LUT-Register 4-input ...

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... Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices reg_chain_in datain aclr aclr datain regout sclr latchout sdata regout aclr datain sdata regout reg_chain_out Figure 2–17). The Quartus II Compiler Adaptive Logic Modules lelocal 0 leout 0 a leout 0 b lelocal 1 leout 1 a leout 1 b © February 2009 Altera Corporation ...

Page 63

... Logic Note to Figure 2–17: (1) You can use the combinational or adder logic to implement an unrelated, un-registered function. 1 For more information on register chain interconnect, refer to page 2–20. © February 2009 Altera Corporation (Note 1) From previous ALM within the LAB reg_chain_in labclk adder0 D Q reg0 ...

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... ALMs in the LAB ALM 1 Register chain routing to adjacent ALM's register input ALM 2 Local ALM 3 interconnect ALM 4 ALM 5 ALM 6 ALM 7 ALM 8 ALM 9 ALM 10 chapter in volume 1 of the Stratix III Device Handbook. Adaptive Logic Modules MultiTrack Interconnect in © February 2009 Altera Corporation ...

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... Updated “LAB Control Signals”, and “Carry Chain” Sections. ■ October 2008, version 1.4 Updated New Document Format. ■ © February 2009 Altera Corporation chapter in section 3 of the Quartus II Handbook for Changes Made 2–21 chapter in Summary of Changes — ...

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... November 2006, Initial Release. version 1.0 Stratix III Device Handbook, Volume 1 Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Changes Made Chapter Revision History Summary of Changes — Minor changes. Minor changes. — © February 2009 Altera Corporation ...

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... LAB. R4 interconnects can drive and be driven by DSP blocks and RAM blocks and row IOEs. For LAB interfacing, a primary LAB or LAB neighbor can drive a given R4 © October 2008 Altera Corporation 3. MultiTrack Interconnect in Stratix III Figure 3–1 shows R4 interconnect connections from Devices ® ...

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... C12 column interconnects for high-speed vertical routing through the device Stratix III Device Handbook, Volume 1 Chapter 3: MultiTrack Interconnect in Stratix III Devices (Note 1), (2) Adjacent LAB can C4 and C12 Drive onto Another Column Interconnects (1) LAB's R4 Interconnect LAB MLAB LAB Neighbor Neighbor Column Interconnects R4 Interconnect Driving Right © October 2008 Altera Corporation ...

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... IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. © October 2008 Altera Corporation Figure 3–2 shows the shared arithmetic chain, carry chain, and register ...

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... Each C4 interconnect can drive either up or down four rows. Stratix III Device Handbook, Volume 1 Chapter 3: MultiTrack Interconnect in Stratix III Devices (Note 1) Local Interconnect Column Interconnects C4 Interconnects Drives Local and R4 Interconnects up to Four Rows C4 Interconnects Driving Up LAB C4 Interconnects Driving Down © October 2008 Altera Corporation ...

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... Row IOE — — — Notes to Table 3–1: (1) Except column IOE local interconnects. (2) Row IOE local interconnects. (3) Column IOE local interconnects. © October 2008 Altera Corporation Destination — — — — — — — — — — — ...

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... MLAB RAM block has equal opportunity for access and performance to and from LABs on either its left or right side. row interface. Stratix III Device Handbook, Volume 1 Chapter 3: MultiTrack Interconnect in Stratix III Devices Hops Figure 3–4 shows the MLAB RAM block to LAB Memory Block Interface Number of LABs 34 96 160 © October 2008 Altera Corporation ...

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... M9K RAM Block are possible from the left adjacent LABs and another 20 possible from the right adjacent LAB. M9K RAM block outputs can also connect to left and right LABs through direct link interconnect. M9K RAM block to logic array interface. © October 2008 Altera Corporation dataout MLAB clocks ...

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... Stratix III Device Handbook, Volume 1 Chapter 3: MultiTrack Interconnect in Stratix III Devices 36 dataout M9K 20 datain byte control enable signals clocks address LAB Row Clocks Memory Block Interface R4 Interconnects Direct link interconnect to adjacent LAB Direct link interconnect from adjacent LAB Figure 3–6 © October 2008 Altera Corporation ...

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... LAB through direct link interconnects and eighteen can drive to the right LAB though direct link interconnects. All 36 outputs can drive to R4 and C4 routing interconnects. Outputs can drive right- or left-column routing. Figure 3–8 show the DSP block interfaces to LAB rows. © October 2008 Altera Corporation R4 Interconnects M144K Block ...

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... Chapter 3: MultiTrack Interconnect in Stratix III Devices DSP Block OA[17..0] R4, C4 & Direct OB[17..0] Link Interconnects A1[35..0] B1[35..0] OC[17..0] OD[17..0] A2[35..0] B2[35..0] OE[17..0] OF[17..0] A3[35..0] B3[35..0] OG[17..0] OH[17..0] A4[35..0] B4[35..0] DSP Block Interface R4, C4 & Direct Link Interconnects © October 2008 Altera Corporation ...

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... There are up to four IOEs per row I/O block and four IOEs per column I/O block. The row I/O blocks drive row, column, or direct link interconnects. The column I/O blocks drive column interconnects. the logic array. © October 2008 Altera Corporation Direct Link Outputs to Adjacent LABs R4 Interconnects ...

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... Stratix III Device Handbook, Volume 1 Chapter 3: MultiTrack Interconnect in Stratix III Devices I/O Block Connections to Interconnect I/O Block Local Interconnect 64 Data & Control Signals from Logic Array 64 Horizontal I/O Block Horizontal I/O Block Contains up to Four IOEs © October 2008 Altera Corporation ...

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... DSP blocks, and IOEs. These blocks communicate with themselves and one another through the MultiTrack interconnect structures. The Quartus II compiler automatically routes critical design paths on faster interconnects to improve design performance and optimize the device resources. © October 2008 Altera Corporation Vertical I/O Block 52 IO_dataina[3:0] ...

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... Added live links for references. ■ November 2006, Initial Release. version 1.0 Stratix III Device Handbook, Volume 1 Chapter 3: MultiTrack Interconnect in Stratix III Devices Changes Made Chapter Revision History Summary of Changes — Minor formatting changes. — © October 2008 Altera Corporation ...

Page 81

... ROM mode) or 320 (including parity bits) (in other modes) Configurations (depth × width) (1) Parity bits © May 2009 Altera Corporation 4. TriMatrix Embedded Memory Blocks in ® III FPGA designs. TriMatrix memory Plug-In Manager. You can stitch together multiple blocks of the same MLABs M9K Blocks ...

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... Overview M144K Blocks Outputs cleared Output registers v Write and Read: Rising clock edges Outputs set to old or new data Outputs set to old data or don’t care Built-in support in ×64 wide SDP mode or soft IP support via Quartus II software © May 2009 Altera Corporation ...

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... The unwritten bytes retain the previous written value. The write enable (wren) signals, along with the byte-enable (byteena) signals, control the RAM blocks’ write operations. © May 2009 Altera Corporation Total Dedicated RAM Bits M144K ...

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... Stratix III Device Handbook, Volume 1 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices a1 a2 ABCD 01 11 ABFF FFFF ABXX XXCD ABCD FFCD ABFF ABCD Overview XXXX XX FFCD ABCD ABFF FFCD ABCD ABFF FFCD ABCD © May 2009 Altera Corporation ...

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... When the memory blocks are configured in dual-port mode, each port has its own independent address clock enable. The default value for the address clock enable signals is low (disabled). © May 2009 Altera Corporation ...

Page 86

... Stratix III Device Handbook, Volume 1 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices 1 address[0] 0 address[0] register 1 address[N] register address[N] 0 addressstall clock dout0 doutn dout1 dout0 dout1 Overview address[0] address[ dout4 dout4 dout5 © May 2009 Altera Corporation ...

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... Figure 4–5. Stratix III Address Clock Enable during Write Cycle Waveform for M9K and M144K inclock a0 wraddress data 00 wren addressstall latched address an (inside memory) XX contents at a0 contents at a1 contents at a2 contents at a3 contents at a4 contents at a5 © May 2009 Altera Corporation ...

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... RAM outputs via the output latch asynchronous clear. The functional waveform in functionality. Stratix III Device Handbook, Volume 1 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Overview “Memory Modes” on Figure 4–7 shows this © May 2009 Altera Corporation ...

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... Single error and fixed Double error and no fix Illegal Illegal Illegal Illegal 1 You cannot use the byte-enable feature when ECC is engaged. 1 Read during write “old data” mode is not supported when ECC is engaged. © May 2009 Altera Corporation RAM Megafunction User Guide. eccstatus[2] eccstatus[ ...

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... Stratix III Device Handbook, Volume 1 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices RAM Array 64 Figure 4–9 Overview 8 SECDED Comparator Encoder Flag Error Generator Locator 64 3 Status Flags Error Correction Block 64 Data Output shows the single-port RAM © May 2009 Altera Corporation ...

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... Mode) Port Width Port Width Configurations Note to Table 4–4: (1) Configurations of 64 × × × 10, 32 × 16, 32 × 18, and 32 × 20 are supported by stitching multiple MLAB blocks. © May 2009 Altera Corporation (Note 1) data[ ] address[ ] wren byteena[] addressstall inclock clockena rden aclr for more details on this behavior ...

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... Figure 4–12 Stratix III Device Handbook, Volume 1 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices a0(old data a1(old data (old data ) (old data) shows the simple dual-port configuration. Overview © May 2009 Altera Corporation ...

Page 93

... May 2009 Altera Corporation (Note 1) data[ ] wraddress[ ] wren byteena[] rd_addressstall wr_addressstall wrclock wrclocken aclr shows the mixed width configurations for the M9K blocks in Write Port 2K×4 1K× ...

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... Stratix III Device Handbook, Volume 1 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices dout0 doutn dout0 doutn Overview “Read During Write” on page 4– din4 din5 din6 din4 din5 din6 b2 b3 © May 2009 Altera Corporation ...

Page 95

... May 2009 Altera Corporation Figure 4–15 shows the true dual-port RAM configuration. (Note 1) data_a[ ] data_b[ ] address_a[ ] address_b[] wren_a wren_b byteena_a[] byteena_b[] addressstall_a addressstall_b clock_a ...

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... Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Write Port 8K×16 4K× — — — — — — for more details about this behavior. Overview 16K×9 8K×18 4K×36 — — — — — — — — — “Read During Write” © May 2009 Altera Corporation ...

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... The size of a shift register (w × m × determined by the input data width (w), the length of the taps (m), and the number of taps (n). You can cascade memory blocks to implement larger shift registers. © May 2009 Altera Corporation ...

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... For more information about implementing FIFO buffers, refer to the Dual-Clock FIFO Megafunctions User 1 MLABs do not support mixed-width FIFO mode. Stratix III Device Handbook, Volume 1 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Number of Taps W W Guide. © May 2009 Altera Corporation Overview Single- and ...

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... This applies to both read and write operations. 1 Altera recommends using a memory block clock that comes through global clock routing from an on-chip PLL set to 50% output duty cycle to achieve the maximum memory block performance. Use Quartus II to report timing for this and other memory block clocking schemes ...

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... Therefore, you must implement conflict resolution logic external to the memory block to avoid address conflicts. Stratix III Device Handbook, Volume 1 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Logic Array Blocks and chapter in volume 1 of the Stratix III Device © May 2009 Altera Corporation Design Considerations ...

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... Using the don’t care mode increases the flexibility in the type of memory block used, provided you do not assign block type when instantiating a memory block. You may also get potential performance gain by selecting the don’t care mode. © May 2009 Altera Corporation Figure 4–18 shows the difference between the ...

Page 102

... XX23 B4XX XXXX DDDD (Note A123 B456 C789 DDDD (old data) B423 A1(old data) old old , and (old data) is the old data at address A0 A1 Design Considerations 0B 11 EEEE FFFF EEEE FFFF A1 11 EEEE FFFF DDDD EEEE A1 . © May 2009 Altera Corporation ...

Page 103

... Manager when instantiating a memory in your design. Even if a memory is pre-initialized (for example .mif file), it still powers up with its outputs cleared. f For more information about .mif files, refer to the the Quartus II © May 2009 Altera Corporation Guide. (Note 1) A0 AAAA BBBB CCCC ...

Page 104

... You can independently configure each embedded memory block single- or dual-port RAM, FIFO, ROM, or shift register via the Quartus II MegaWizard Plug-In Manager software. Stratix III Device Handbook, Volume 1 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Sheet. that is published for M144K blocks in MAX © May 2009 Altera Corporation Conclusion ...

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... Added live links for references. ■ May 2007, Updated Table 4–2, Table 4–9. version 1.1 November 2006, Initial Release. version 1.0 © May 2009 Altera Corporation Changes Made 4–1. and “Simple Dual-Port Mode” 4–25 Summary of Changes — — ...

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... Stratix III Device Handbook, Volume 1 Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices Chapter Revision History © May 2009 Altera Corporation ...

Page 107

... Cascading 44-bit output bus to propagate output results from one block to the next block without external logic support ■ Rich and flexible arithmetic rounding and saturation units © March 2010 Altera Corporation 5. DSP Blocks in Stratix III Devices Stratix III Device Handbook, Volume 1 ...

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... Figure 5–1. © March 2010 Altera Corporation ...

Page 109

... Note that for all signed numbers, input and output data is represented in 2’s complement format only. Equation 5–1. Multiplier Equation Figure 5–2. Basic Two-Multiplier Adder Building Block A0[17..0] B0[17..0] A1[17..0] B1[17..0] © March 2010 Altera Corporation Half-DSP Block Half-DSP Block Full DSP Block P[36.. [17..0] × B [17..0] ± ...

Page 110

... Z[37.. [36.. [43.. [43..0] ± n-1 provides a sum of four 18-bit × 18-bit multiplication operations Equation 5–3 provides a four 18-bit × 18-bit Chapter 5: DSP Blocks in Stratix III Devices Simplified DSP Operation [36..0] 1 [37..0] n Figure 5–3. © March 2010 Altera Corporation ...

Page 111

... FIR and vector multiplication capability. To support single-channel type FIR filters efficiently, you can configure one of the multiplier input’s registers to form a tap delay line input, saving resources and providing higher system performance. © March 2010 Altera Corporation 5–5 44 Result Figure 5– ...

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... Stratix III Device Handbook, Volume 1 From Previous Half-Block DSP Next Half-Block DSP Figure 5–4 is the optional Rounding and Saturation Unit (RSU). This Figure 5–6. Chapter 5: DSP Blocks in Stratix III Devices Simplified DSP Operation 44 Result 44 Figure 5–5. A more detailed © March 2010 Altera Corporation ...

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... Chapter 5: DSP Blocks in Stratix III Devices Simplified DSP Operation Figure 5–5. Stratix III Full DSP Block Summary 144 Input Data 144 Input Data © March 2010 Altera Corporation From Previous Half-Block DSP Top Half-DSP Block Bottom Half-DSP Block To Next Half-Block DSP 5– ...

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... Stage Stage Adder Add/Sub Add/Acc No No — — — — Yes No — — — — — — Both — Yes Yes Both Add Only No No — Add Only Yes Yes Both Both No — — — © March 2010 Altera Corporation ...

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... DSP blocks and not from general routing. (2) Block output for accumulator overflow and saturate overflow. (3) Block output for saturation overflow of chainout. (4) When the chainout adder is not in use, the second adder register banks are known as output register banks. © March 2010 Altera Corporation signa signb zero_loopback ...

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... A feature of the input register bank is to support a tap delay line. Therefore, the top leg of the multiplier input (A) could be driven from general routing or from the cascade chain, as shown in Stratix III Device Handbook, Volume 1 Chapter 5: DSP Blocks in Stratix III Devices Figure 5–7. © March 2010 Altera Corporation DSP Block Resource Descriptions ...

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... DSP blocks. The dedicated shift register chain spans a single column, but you can implement longer shift register chains requiring multiple columns using the regular FPGA routing resources. © March 2010 Altera Corporation clock[3..0] ena[3..0] signa aclr[3 ...

Page 118

... Unsigned (logic 0) Signed (logic 1) Chapter 5: DSP Blocks in Stratix III Devices DSP Block Resource Descriptions Figure 5–6. In loopback 18 × × 36 Double — — v — — for details. “Independent Table 5–4 lists the Result Unsigned Signed Signed Signed © March 2010 Altera Corporation ...

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... You cannot use the second-stage adder independently from the multiplier and first-stage adder. © March 2010 Altera Corporation “Two-Multiplier Adder Sum Mode” on Figure 5–6. There are four first-stage adders in a DSP block (two 5–6. Pipeline registers increase the DSP block’s maximum 5– ...

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... Refer to on page 5–15 Stratix III Device Handbook, Volume 1 “Operational Mode Descriptions” on for details. Chapter 5: DSP Blocks in Stratix III Devices DSP Block Resource Descriptions “Operational Mode Descriptions” © March 2010 Altera Corporation ...

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... Figure 5–8. 18-Bit Independent Multiplier Mode for Half-DSP Block clock[3..0] ena[3..0] aclr[3..0] 18 dataa_0[17..0] 18 datab_0[17..0] 18 dataa_1[17..0] 18 datab_1[17..0] © March 2010 Altera Corporation Figure 5–8, Figure 5–9, and signa signb output_round output_saturate Half-DSP Block 5–15 Figure 5–10 show the DSP block in ...

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... Stratix III Device Handbook, Volume 1 signa signb Half-DSP Block Chapter 5: DSP Blocks in Stratix III Devices Operational Mode Descriptions 24 result_0 result_1 result_2[ ] © March 2010 Altera Corporation ...

Page 123

... You can use the pipeline registers within the DSP block to pipeline the multiplier result, increasing the performance of the DSP block. 1 The round and saturation logic unit is supported for the 18-bit independent multiplier mode only. © March 2010 Altera Corporation signa signb 18 18 ...

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... Figure 5–11. 36-Bit Independent Multiplier Mode for Half-DSP Block clock[3..0] ena[3..0] aclr[3..0] dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] dataa_0[35..18] datab_0[17..0] dataa_0[17..0] datab_0[17..0] Half-DSP Block Stratix III Device Handbook, Volume 1 Chapter 5: DSP Blocks in Stratix III Devices signa signb + + + Operational Mode Descriptions Figure 5–11. 72 result[ ] © March 2010 Altera Corporation ...

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... This is shown in Figure 5–12. Double Mode for Half-DSP Block clock[3..0] ena[3..0] aclr[3..0] dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] dataa_0[35..18] datab_0[17..0] dataa_0[17..0] datab_0[17..0] Half-DSP Block © March 2010 Altera Corporation Figure 5–12 and Figure 5–13. signa signb + + + 5–19 72 result[ ] Stratix III Device Handbook, Volume 1 ...

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... Stratix III Device Handbook, Volume 1 Chapter 5: DSP Blocks in Stratix III Devices signa signb Two Multiplier Adder Mode 36 + Double Mode Mode 72 Unsigned Multiplier Operational Mode Descriptions 108 result[ ] © March 2010 Altera Corporation ...

Page 127

... The two-multiplier adder mode supports the round and saturation logic unit. You can use the pipeline registers and output registers within the DSP block to pipeline the multiplier-adder result, increasing the performance of the DSP block. © March 2010 Altera Corporation 5–21 Stratix III Device Handbook, Volume 1 ...

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... Figure 5–14. Two-Multiplier Adder Mode for Half-DSP Block clock[3..0] ena[3..0] aclr[3..0] dataa_0[17..0] datab_0[17..0] dataa_1[17..0] datab_1[17..0] dataa_2[17..0] datab_2[17..0] dataa_3[17..0] datab_3[17..0] Half-DSP Block Stratix III Device Handbook, Volume 1 Chapter 5: DSP Blocks in Stratix III Devices signa signb output_round output_saturate + + Operational Mode Descriptions overflow result_0[ ] result_1[ ] © March 2010 Altera Corporation ...

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... Chapter 5: DSP Blocks in Stratix III Devices Operational Mode Descriptions Figure 5–15. Loopback Mode for Half-DSP Block clock[3..0] ena[3..0] aclr[3..0] zero_loopback dataa_0[17..0] loopback datab_0[17..0] dataa_1[17..0] datab_1[17..0] Half-DSP Block © March 2010 Altera Corporation signa signb output_round output_saturate + Stratix III Device Handbook, Volume 1 5–23 overflow result[ ] ...

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... Stratix III Device Handbook, Volume 1 Chapter 5: DSP Blocks in Stratix III Devices (a + jb) × jd) = ((a × c) – (b × d)) + j((a × × c)) Figure 5–16 shows an 18-bit complex signa signb 36 − Operational Mode Descriptions Equation 5– − (Real Part − (Imaginary Part) © March 2010 Altera Corporation ...

Page 131

... The four-multiplier adder mode supports the round and saturation logic unit. You can use the pipeline registers and output registers within the DSP block to pipeline the multiplier-adder result, increasing the performance of the DSP block. © March 2010 Altera Corporation and Equation 5– ...

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... Equation 5–5. High Precision Multiplier Adder Equation Stratix III Device Handbook, Volume 1 Chapter 5: DSP Blocks in Stratix III Devices Z[54.. [53.. [53..0] where A[17..0] ´ B[35..0] and P = C[17..0] ´ D[35.. Operational Mode Descriptions Figure 5–18, the DSP © March 2010 Altera Corporation ...

Page 133

... Operational Mode Descriptions Figure 5–18. Four-Multiplier Adder Mode for Half-DSP Block clock[3..0] ena[3..0] aclr[3..0] dataA[17..0] dataB[17..0] dataA[17..0] dataB[35..18] dataC[17..0] dataD[17..0] dataC[17..0] dataD[35..0] Half-DSP Block © March 2010 Altera Corporation signa signb P 0 << <<18 5–27 overflow Z[54..0] Stratix III Device Handbook, Volume 1 ...

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... Half-DSP Block Stratix III Device Handbook, Volume 1 Chapter 5: DSP Blocks in Stratix III Devices Equation 5–3. Figure 5–19 shows the DSP block configured signa signb output_round output_saturate Operational Mode Descriptions chainout_sat_overflow 44 result[ ] © March 2010 Altera Corporation ...

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... Two control signals rotate and shift_right together with the signa and signb signals, determining the shifting operation. Examples of shift operations are listed in Table 5–5 on page © March 2010 Altera Corporation II to perform the dynamic shift and rotate operation. ® 5–31. ...

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... Figure 5–20. Shift Operation Mode for Half-DSP Block clock[3..0] ena[3..0] aclr[3..0] dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] dataa_0[35..18] datab_0[17..0] dataa_0[17..0] datab_0[17..0] Half-DSP Block Stratix III Device Handbook, Volume 1 Chapter 5: DSP Blocks in Stratix III Devices signa signb rotate shift_right © March 2010 Altera Corporation Operational Mode Descriptions 32 result[ ] ...

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... LSB is zero (even). Table 5–6. Example of Round-To-Nearest-Even Mode 6- to 4-bits Rounding 010111 001101 001010 001110 110111 101101 110110 110010 © March 2010 Altera Corporation (Note 1) Shift_right Rotate A-input 0 0 0xAABBCCDD 1 0 0xAABBCCDD 0 0 ...

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... Operational Mode Descriptions Round-To-Nearest-Even ⇒ 010111 0110 ⇒ 001101 0011 ⇒ 001010 0010 ⇒ 001110 0100 ⇒ 110111 1110 ⇒ 101101 1011 ⇒ 110110 1110 ⇒ 110010 1100 –1. Symmetrical saturation will limit Asymmetric SAT Result 7FFFFFFFFh 800000000h © March 2010 Altera Corporation ...

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... Likewise, the functionality of the saturation logic unit is in the format of: Result = SAT[S(A × B)], when used for an accumulation type of operation. If both the round and saturation logic units are used for an accumulation type of operation, the format is: Result = SAT[RND[S(A × B)]] © March 2010 Altera Corporation User defined RND Positions (bit 21- 5– ...

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... Total Signals per Half-block clock0 clock1 DSP-block-wide clock signals clock2 clock3 Stratix III Device Handbook, Volume 1 Chapter 5: DSP Blocks in Stratix III Devices lists the dynamic signals for the DSP block. Function Operational Mode Descriptions Count © March 2010 Altera Corporation ...

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... Refer to for details. The B input of the multiplier feeds from the general routing. You can scan in the data in 18-bit parallel form and multiply it by the 18-bit input bus from general routing in each cycle. © March 2010 Altera Corporation Function Equation N 1 – ...

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... For a complete FIR, the results per individual Four-Multiplier Adder can be combined in either a tree or chained cascade manner. Using external logic and adders, you can very easily implement a tree summation, as shown in Stratix III Device Handbook, Volume 1 Chapter 5: DSP Blocks in Stratix III Devices Application Examples Figure 5–22. Figure 5–22. © March 2010 Altera Corporation ...

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... One of the two second-stage adders is used to add the current Four-Multiplier Adder. The second second-stage adder takes the output of the first second-stage adder and adds it to the adjacent half DSP block of the Four-Multiplier Adder result. © March 2010 Altera Corporation signa signb ...

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... Delay Register datab_4[17..0] datab_5[17..0] datab_6[17..0] datab_7[17..0] Stratix III Device Handbook, Volume 1 Chapter 5: DSP Blocks in Stratix III Devices signa signb chainout_round chainout_saturate zero_chainout chainout_sat_overflow + Zero + + + Half-DSP Block + + + + Half-DSP Block Application Examples 44 result[ ] © March 2010 Altera Corporation ...

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... Four-Multiplier Mode with independent inputs. In most cases, only the final stage FIR tap with the rounding and saturation unit is deployed. © March 2010 Altera Corporation and Figure 5–23. The main difference is that the input cascade Figure 5– ...

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... You can use the Stratix III DSP block to form the core of a complex FFT butterfly very efficiently. Stratix III Device Handbook, Volume 1 Chapter 5: DSP Blocks in Stratix III Devices signa signb chainout_round chainout_saturate zero_chainout chainout_sat_overflow Zero Half-DSP Block Half-DSP Block Application Examples 44 result[ ] © March 2010 Altera Corporation ...

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... A0 RAM X[k,1] A1 RAM X[k,2] A2 RAM X[k,3] A3 Software Support Altera provides two distinct methods for implementing various modes of the DSP block in a design: instantiation and inference. Both methods use the following Quartus II megafunctions: ■ LPM_MULT ALTMULT_ADD ■ ALTMULT_ACCUM ■ ■ ALTFP_MULT You can instantiate the megafunctions in the Quartus II software to use the DSP block. ...

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... Added two new figures, Figure 5–10 and Figure 5–11. Updated Table 5–1 and Table 5–5. Deleted Table 5-10. Added sections “Double Multiplier” and “Referenced Documents”. Clarification added for “Shift Modes” on page 5–28. Chapter 5: DSP Blocks in Stratix III Devices Chapter Revision History © March 2010 Altera Corporation ...

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... Stratix clocking resources, in combination with the clock synthesis precision provided by the PLLs, provide a complete clock management solution. The Altera software compiler automatically turns off clock networks not used in the design, thereby reducing the overall power consumption of the device. ...

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... Stratix III Device Handbook, Volume 1 Chapter 6: Clock Networks and PLLs in Stratix III Devices # of Resources Available 80/104 (4) Figure 6–1 to Figure CLK[12..15 GCLK[12..15] GCLK[0..3] GCLK[8..11] GCLK[4.. CLK[4..7] Clock Networks in Stratix III Devices Source of Clock Resource 16 GCLKs + 64 RCLKs / 16 GCLKs + 88 RCLKs 6– CLK[8..11 © July 2010 Altera Corporation ...

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... EP3SL200, EP3SE260, and EP3SL340 devices contain 88 RCLKs. Figure 6–2. Regional Clock Networks (EP3SL50, EP3SL70, and EP3SE50 Devices) L2 CLK[0..3] Figure 6–3. Regional Clock Networks (EP3SL110, EP3SL150, EP3SE80, and EP3SE110 Devices) L2 CLK[0..3] L3 © July 2010 Altera Corporation Figure 6–2 to Figure 6–4 CLK[12..15] T1 RCLK[54..63] RCLK[44..53] RCLK[0..5] RCLK[38..43] ...

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... RCLK[6..11] RCLK[32..37] RCLK[64..69] RCLK[70..75] RCLK[12..21] RCLK[22..31 CLK[4..7] Figure 6–5 CLK[12..15] T1 PCLK[0..13] PCLK[42..55 PCLK[14..27] PCLK[28..41] B1 CLK[4..7] Clock Networks in Stratix III Devices (Note CLK[8..11 Table 6–9 on page 6–13 for connectivity. to Figure 6–9 are a collection of R2 CLK[8..11] © July 2010 Altera Corporation ...

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... Chapter 6: Clock Networks and PLLs in Stratix III Devices Clock Networks in Stratix III Devices Figure 6–6. Periphery Clock Networks (EP3SL110, EP3SL150, EP3SE80, and EP3SE110 Devices) L2 CLK[0..3] L3 Figure 6–7. Periphery Clock Networks (EP3SL200 Devices CLK[0.. © July 2010 Altera Corporation CLK[12..15 PCLK[0..10] PCLK[77..87] PCLK[11..21] PCLK[66..76 PCLK[22..32] PCLK[55..65] PCLK[33..43] PCLK[44 ...

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... Chapter 6: Clock Networks and PLLs in Stratix III Devices CLK[12..15 PCLK[0..13] PCLK[98..111] PCLK[14..27] PCLK[84..97 PCLK[28..41] PCLK[70..83] PCLK[42..55] PCLK[56..69 CLK[4..7] CLK[12..15 PCLK[0..15] PCLK[116..131] PCLK[16..32] PCLK[99..115 PCLK[33..49] PCLK[82..98] PCLK[50..65] PCLK[66..81 CLK[4..7] Clock Networks in Stratix III Devices R1 R2 CLK[8..11 CLK[8..11 © July 2010 Altera Corporation ...

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... CLK[15..0] for high fan-out control signals such as asynchronous clears, presets, and clock enables for protocol signals such as TRDY and IRDY for PCI through global or regional clock networks. © July 2010 Altera Corporation Figure 6–10 shows the Clock pins or PLL outputs ...

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... July 2010 Altera Corporation ...

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... RCLK45 — — — RCLK46 — — — RCLK47 — — — RCLK48 — — — RCLK49 © July 2010 Altera Corporation CLK (p/n Pins — — — — — — — — — — — — — ...

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... July 2010 Altera Corporation ...

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... CLK3 — CLK4 — CLK5 — CLK6 — CLK7 — CLK8 — CLK9 — CLK10 — CLK11 — CLK12 © July 2010 Altera Corporation CLK (p/n Pins — — — — — — — — — — — — — — ...

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... July 2010 Altera Corporation ...

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... Once programmed, this block cannot be changed without loading a new configuration file (.sof or .pof). The Quartus II software automatically sets the multiplexer select signals depending on the clock sources selected in the design. © July 2010 Altera Corporation PLL Number ...

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... Stratix III Device Handbook, Volume 1 Chapter 6: Clock Networks and PLLs in Stratix III Devices (1) 4 clk[n+3..n] (2) Adjacent PLL output (1) 4 PLL_<L1/L4/R1/R4>_CLK (1) GCLK/RCLK (2) 4 CLK[0..3] or CLK[8..11] (3) 4 Clock Networks in Stratix III Devices inclk0 To the clock switchover block inclk1 inclk0 inclk1 © July 2010 Altera Corporation ...

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... The unused global and regional clock networks are automatically powered down through configuration bit settings in the configuration file (.sof or .pof) generated by the © July 2010 Altera Corporation Figure 6–14 show the global clock and regional clock select blocks, CLKp ...

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... Stratix III Device Handbook, Volume 1 Chapter 6: Clock Networks and PLLs in Stratix III Devices PLL Counter Outputs Static Clock Select (1) Enable/ Disable Internal Logic IOE (2) Internal Logic Static Clock Select (1) PLL_<#>_CLKOUT pin Clock Networks in Stratix III Devices Figure 6–13 and © July 2010 Altera Corporation ...

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... AND gate with R2 bypassed output of AND gate with R2 not bypassed Note to Figure 6–17: (1) You can use the clkena signals to enable or disable the global and regional networks or the PLL_<#>_CLKOUT pins. © July 2010 Altera Corporation (1) ( Figure 6–17 6–17 GCLK/ RCLK/ PLL_< ...

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... PLLs in Stratix III Devices — — — — v — — — — — — — — — — — — — — — — © July 2010 Altera Corporation ...

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... The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For degree increments, the Stratix III device can shift all output frequencies in increments of at least 45 degrees. Smaller degree increments are possible depending on the frequency and divide parameters. © July 2010 Altera Corporation Table 6–11 lists the features of the Top/Bottom and Stratix III Top/Bottom PLLs ...

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... Stratix III Device Handbook, Volume 1 Chapter 6: Clock Networks and PLLs in Stratix III Devices Top/Bottom PLLs Top/Bottom PLLs CLK[12..15 CLK[4..7] Top/Bottom PLLs Top/Bottom PLLs PLLs in Stratix III Devices R1 PLL_R1_CLK Left/Right PLLs R2 CLK[8..11] R3 Left/Right PLLs R4 PLL-R4_CLK © July 2010 Altera Corporation ...

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... I/O, 1 differential external feedback input (FBp/FBn), or ■ 1 single-ended external feedback input (FBp) ■ 3rd pair: 2 single-ended I differential input © July 2010 Altera Corporation ) is equal to (m) times the input reference clock (f VCO ) to the PFD is equal to the input clock (f REF ) applied to one input of the PFD is FB that is applied to the other input of the PFD ...

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... Chapter 6: Clock Networks and PLLs in Stratix III Devices clkena4 (3) clkena2 (3) clkena3 (3) clkena5 (3) PLL_<#>_CLKOUT3 PLL_<#>_FBp/CLKOUT1 (1), (2) PLL_<#>_FBn/CLKOUT2 (1), (2) and Figure 6–21. Therefore, one counter or frequency can drive PLLs in Stratix III Devices Internal Logic (1), (2) PLL_<#>_CLKOUT4 (1), (2) © July 2010 Altera Corporation ...

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... Stratix III PLLs can also drive out to any regular I/O pin through the global or regional clock network. You can use the external clock output pins as user I/O pins if external PLL clocking is not needed. © July 2010 Altera Corporation Internal Logic C0 C1 ...

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... Dedicated pin, adjacent PLL, GCLK, or RCLK network Pin LVSDCLK Logic array or I/O pin PLLs in Stratix III Devices Physical Pin Internal Clock Signal Signal driven to internal logic or I/O pins Destination N counter N counter PFD Clock switchover circuit © July 2010 Altera Corporation ...

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... PLL. If this signal is high, inclk1 drives the PLL. Output of the last shift register in scandataout the scan chain. © July 2010 Altera Corporation Source Logic array Logic array Logic array Logic array Logic array or I/O pin Logic array or I/O pins ...

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... M counter Availability Top/Bottom PLLs Yes Yes Yes Yes (2) Yes ( Plug-in Manager when using PLLs in external feedback mode. PLLs in Stratix III Devices Destination Logic array Logic array Logic array Left/Right PLLs Yes Yes Yes Yes Yes (1) Yes © July 2010 Altera Corporation ...

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... Set the input pin to register delay chain within the IOE to zero in the Quartus II software for all data pins clocked by a source-synchronous mode PLL. Also, all data pins must use the PLL COMPENSATED logic option in the Quartus II software. © July 2010 Altera Corporation Data pin PLL reference clock ...

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... Chapter 6: Clock Networks and PLLs in Stratix III Devices Phase Aligned PLL Reference Clock at the Input Pin PLL Clock at the Register Clock Port (1) Figure 6–26 shows an example waveform of the PLL clocks’ phase PLLs in Stratix III Devices Figure 6–25 shows an example © July 2010 Altera Corporation ...

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... The bi-directional I/O pin that you instantiate in your design should always be assigned a single-ended I/O standard. Figure 6–27. Zero-Delay Buffer Mode in Stratix III PLLs inclk ÷n © July 2010 Altera Corporation Phase Aligned PLL Reference Clock at the Input Pin PLL Clock at the ...

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... Register Clock Port Dedicated PLL Clock Outputs (1) Figure 6–29 shows the EFB mode implementation in ÷C0 VCO PFD CP/LF ÷C1 ÷m PLLs in Stratix III Devices Figure 6–30. Aligning these clocks PLL_<#>_CLKOUT# PLL_<#>_CLKOUT# fbout external board fbin trace © July 2010 Altera Corporation ...

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... The Quartus II software automatically chooses the appropriate scaling factors according to the input frequency, multiplication, and division values entered into the ALTPLL megafunction. © July 2010 Altera Corporation Phase Aligned PLL Reference Clock at the Input Pin ...

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... Combining the programmable duty cycle with programmable phase shift allows the generation of precise non-overlapping clocks. Stratix III Device Handbook, Volume 1 Chapter 6: Clock Networks and PLLs in Stratix III Devices PLLs in Stratix III Devices from preceding post-scale counter Cn (1) © July 2010 Altera Corporation Figure 6–31. ...

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... Altera recommends that you use the areset and locked signals in your designs to control and observe the status of your PLL. Clock Switchover The clock switchover feature allows the PLL to switch between two reference input clocks ...

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... Chapter 6: Clock Networks and PLLs in Stratix III Devices Switchover Clock State Sense Machine clksw Clock Switch Control Logic n Counter PFD refclk Figure 6–32. In this case, inclk1 becomes the PLLs in Stratix III Devices clkbad0 clkbad1 activeclock clkswitch fbclk © July 2010 Altera Corporation ...

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... PLL may lose lock after the switchover is completed and need time to re-lock. 1 Altera recommends resetting the PLL using the areset signal to maintain the phase relationships between the PLL input and output clocks when using clock switchover. When using automatic switchover mode, the clkbad[0] and clkbad[1] signals indicate the status of the two clock inputs ...

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... If the clock is not available, the state machine waits until the clock is available. Stratix III Device Handbook, Volume 1 Chapter 6: Clock Networks and PLLs in Stratix III Devices PLLs in Stratix III Devices (Note 1) © July 2010 Altera Corporation ...

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... Both inclk0 and inclk1 must be running when the clkswitch signal goes high to instantiate the manual clock switchover event. Failing to meet this requirement causes the clock switchover to not function properly. © July 2010 Altera Corporation shows the block diagram of the manual switchover circuit. n Counter muxout refclk Guide ...

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... Stratix III Device Handbook, Volume 1 Chapter 6: Clock Networks and PLLs in Stratix III Devices shows how the VCO frequency gradually decreases when the current Switchover Occurs PLLs in Stratix III Devices VCO Tracks Secondary Clock © July 2010 Altera Corporation ...

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... Figure 6–37. Open- and Closed-Loop Response Bode Plots Open-Loop Reponse Bode Plot 0 dB Gain Closed-Loop Reponse Bode Plot Gain © July 2010 Altera Corporation Figure 6–37 shows, these points correspond to approximately the same Increasing the PLL's bandwidth in effect pushes the open loop response out. Frequency Frequency 6– ...

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... C , and the charge pump current Figure 6–38. Loop Filter Programmable Components Stratix III Device Handbook, Volume 1 Chapter 6: Clock Networks and PLLs in Stratix III Devices , R, C) values to achieve the desired PFD I DN PLLs in Stratix III Devices . © July 2010 Altera Corporation ...

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... VCO and also has the C value for the counter set to one. The CLK1 signal is also divided this case, the two clocks are offset by 3Φ off the 0phase from the VCO but has the C value for the counter set to three. This arrangement creates a delay of 2Φ © July 2010 Altera Corporation ...

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... This approach eliminates the need to regenerate a configuration file with the new PLL settings. Stratix III Device Handbook, Volume 1 Chapter 6: Clock Networks and PLLs in Stratix III Devices t VCO ) delays in real time by changing the PLL output clock phase CO PLLs in Stratix III Devices © July 2010 Altera Corporation ...

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... This figure shows the corresponding scan register for the counter is physically located after the VCO. 1 The counter settings are updated synchronously to the clock frequency of the individual counters. Therefore, all counters are not updated simultaneously. © July 2010 Altera Corporation cp PFD LF/K/CP (3) /C2 /C1 ...

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... Logic array or I/O pin PLL reconfiguration circuit PLL reconfiguration circuit , settings. cp PLLs in Stratix III Devices Destination PLL reconfiguration circuit PLL reconfiguration circuit PLL reconfiguration circuit PLL reconfiguration circuit Logic array or I/O pins Logic array or I/O pins © July 2010 Altera Corporation ...

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... The PLL implements this duty cycle by transitioning the output clock from high to low on the rising edge of the VCO output clock. However and 6 setting for the high- and low-count values, respectively, would produce an output clock with 40-60% duty cycle. © July 2010 Altera Corporation 6–45 D0 D0_old Dn ...

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... Loop Filter Capacitor Loop Filter Resistor Unused CP/LF Stratix III Device Handbook, Volume 1 Chapter 6: Clock Networks and PLLs in Stratix III Devices Table 6–16 Number of Bits Counter Other ( PLLs in Stratix III Devices lists the number of bits Total ( © July 2010 Altera Corporation ...

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... Left/Right PLLs have the same scan-chain order. The post-scale counters end at Figure 6–43 shows the scan-chain bit-order sequence for post-scale counters in all Stratix III PLLs. Figure 6–43. Scan-Chain Bit-Order Sequence for Post-Scale Counters in Stratix III PLLs DATAOUT 0 1 © July 2010 Altera Corporation Number of Bits Counter — (Note LSB ...

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... Table 6–18, and ), loop-filter resistor (R), and capacitor (C) values cp CP[ LFR[2] LFR[ LFC[ PLLs in Stratix III Devices Table 6–19 list the possible Decimal Value for CP[0] Setting Decimal Value for LFR[0] Setting Decimal Value for Setting © July 2010 Altera Corporation ...

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... PLL on the rising edge of SCANCLK. Selects dynamic phase shift direction; 1= UP; 0= DOWN. Signal PHASEUPDOWN is registered in the PLL on the rising edge of SCANCLK. Logic high enables dynamic phase PHASESTEP shifting. © July 2010 Altera Corporation PLL Scan Chain Bits [0..10] Settings [5] [6] [7] [8] [ ...

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... PLLs in Stratix III Devices Source Destination PLL reconfiguration circuit Logic array or I/O pins [0] Selects 0 All Output Counters 1 M Counter 0 C0 Counter 1 C1 Counter 0 C2 Counter 1 C3 Counter 0 C4 Counter 1 C5 Counter 0 C6 Counter 1 C7 Counter 0 C8 Counter 1 C9 Counter © July 2010 Altera Corporation ...

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... Phasestep pulses must be at least one scanclk cycle apart. f For more information about the ALTPLL_RECONFIG MegaWizard Plug-In Manager, refer to the ALTPLL_RECONFIG Megafunction User © July 2010 Altera Corporation c d PHASEDONE goes low synchronous with SCANCLK /t requirements with respect to scanclk edges. ...

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... Stratix III devices cannot internally generate spread-spectrum clocks. PLL Specifications f For information about PLL timing specifications, refer to the Characteristics of Stratix III Devices Stratix III Device Handbook, Volume 1 Chapter 6: Clock Networks and PLLs in Stratix III Devices PLLs in Stratix III Devices DC and Switching chapter. © July 2010 Altera Corporation ...