EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 15
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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List of Figures
xv
List of Figures
Figure 1–1: Stratix III Device Packaging Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Figure 2–1: Stratix III LAB Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Figure 2–2: Stratix III LAB and MLAB Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Figure 2–3: Direct Link Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Figure 2–4: LAB-Wide Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Figure 2–5: High-Level Block Diagram of the Stratix III ALM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Figure 2–6: Stratix III ALM Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Figure 2–7: ALM in Normal Mode
(Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Figure 2–8: 4 × 2 Crossbar Switch Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Figure 2–9: Input Function in Normal Mode
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Figure 2–10: Template for Supported Seven-Input Functions in Extended LUT Mode . . . . . . . . . . . . . . 2-11
Figure 2–11: ALM in Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Figure 2–12: Conditional Operation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Figure 2–13: ALM in Shared Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Figure 2–14: Example of a 3-Bit Add Utilizing Shared Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Figure 2–15: LUT Register from Two Combinational Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Figure 2–16: ALM in LUT-Register Mode with 3-Register Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Figure 2–17: Register Chain within an LAB
(Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Figure 2–18: Shared Arithmetic Chain, Carry Chain, and Register Chain Interconnects . . . . . . . . . . . . . 2-20
Figure 3–1: R4 Interconnect Connections
(Note
1),
(2)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
Figure 3–2: Shared Arithmetic Chain, Carry Chain, and Register Chain Interconnects . . . . . . . . . . . . . . . 3-3
Figure 3–3: C4 Interconnect Connections
(Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4
Figure 3–4: MLAB RAM Block LAB Row Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7
Figure 3–5: M9K RAM Block LAB Row Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
Figure 3–6: M144K Row Unit Interface to Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
Figure 3–7: High-Level View, DSP Block Interface to Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10
Figure 3–8: Detailed View, DSP Block Interface to Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
Figure 3–9: Row I/O Block Connection to Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
Figure 3–10: Column I/O Block Connection to Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13
Figure 4–1: Stratix III Byte-Enable Functional Waveform for M9K and M144K . . . . . . . . . . . . . . . . . . . . . 4-4
Figure 4–2: Stratix III Byte-Enable Functional Waveform for MLABs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5
Figure 4–3: Stratix III Address Clock Enable Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Figure 4–4: Stratix III Address Clock Enable during Read Cycle Waveform . . . . . . . . . . . . . . . . . . . . . . . . 4-6
Figure 4–5: Stratix III Address Clock Enable during Write Cycle Waveform for M9K and M144K . . . . . 4-7
Figure 4–6: Stratix III Address Clock Enable during Write Cycle Waveform for MLABs . . . . . . . . . . . . . 4-8
Figure 4–7: Output Latch Asynchronous Clear Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9
Figure 4–8: ECC Block Diagram of the M144K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
Figure 4–9: Single-Port Memory
(Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11
Figure 4–10: Timing Waveform for Read-Write Operations (Single-Port Mode) for M9K and M144K . 4-12
Figure 4–11: Timing Waveform for Read-Write Operations (Single-Port Mode) for MLABs . . . . . . . . . 4-12
Figure 4–12: Stratix III Simple Dual-Port Memory
(Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13
Figure 4–13: Stratix III Simple Dual-Port Timing Waveforms for M9K and M144K . . . . . . . . . . . . . . . . . 4-14
Figure 4–14: Stratix III Simple Dual-Port Timing Waveforms for MLABs . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
Figure 4–15: Stratix III True Dual-Port Memory
(Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Figure 4–16: Stratix III True Dual-Port Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17
Figure 4–17: Stratix III Shift-Register Memory Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-18
Figure 4–18: Stratix III Read-During-Write Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-21
© March 2011 Altera Corporation
Stratix III Device Handbook, Volume 1
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