EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 16
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
- Current page: 16 of 456
- Download datasheet (7Mb)
xvi
List of Figures
Figure 4–19: Same Port Read-During-Write: New Data Mode
(Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . 4-22
Figure 4–20: Same Port Read-During-Write: Old Data Mode
(Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-22
Figure 4–21: Mixed Port Read During Write: Old Data Mode
(Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . 4-23
Figure 5–1: Overview of DSP Block Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Figure 5–2: Basic Two-Multiplier Adder Building Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
Figure 5–3: Four-Multiplier Adder and Accumulation Capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-5
Figure 5–4: Output Cascading Feature for FIR Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6
Figure 5–5: Stratix III Full DSP Block Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
Figure 5–6: Half-DSP Block Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9
Figure 5–7: Input Register of Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11
Figure 5–8: 18-Bit Independent Multiplier Mode for Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-15
Figure 5–9: 12-Bit Independent Multiplier Mode for Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16
Figure 5–10: 9-Bit Independent Multiplier Mode for Half-Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
Figure 5–11: 36-Bit Independent Multiplier Mode for Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-18
Figure 5–12: Double Mode for Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-19
Figure 5–13: Unsigned 54 × 54 Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-20
Figure 5–14: Two-Multiplier Adder Mode for Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
Figure 5–15: Loopback Mode for Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-23
Figure 5–16: Complex Multiplier Using Two-Multiplier Adder Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
Figure 5–17: Four-Multiplier Adder Mode for Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-25
Figure 5–18: Four-Multiplier Adder Mode for Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
Figure 5–19: Multiply Accumulate Mode for Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
Figure 5–20: Shift Operation Mode for Half-DSP Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
Figure 5–21: Round and Saturation Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
Figure 5–22: FIR Filter Using Tap-Delay Line Input and Tree Summation of Final Result . . . . . . . . . . . 5-37
Figure 5–23: FIR Filter using Tap-Delay Line Input and Chained Cascade Summation of Final Result 5-38
Figure 5–24: Semi-Parallel FIR Structure Using Chained Cascaded Summation . . . . . . . . . . . . . . . . . . . . 5-40
Figure 5–25: Radix-4 Butterfly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-41
Figure 6–1: Global Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-2
Figure 6–2: Regional Clock Networks (EP3SL50, EP3SL70, and EP3SE50 Devices) . . . . . . . . . . . . . . . . . . 6-3
Figure 6–3: Regional Clock Networks (EP3SL110, EP3SL150, EP3SE80, and EP3SE110 Devices) . . . . . . . 6-3
Figure 6–4: Regional Clock Networks (EP3SL200, EP3SE260, and EP3SL340 Devices)
(Note 1)
. . . . . . . 6-4
Figure 6–5: Periphery Clock Networks (EP3SL50, EP3SL70, and EP3SE50 Devices) . . . . . . . . . . . . . . . . . 6-4
Figure 6–6: Periphery Clock Networks (EP3SL110, EP3SL150, EP3SE80, and EP3SE110 Devices) . . . . . . 6-5
Figure 6–7: Periphery Clock Networks (EP3SL200 Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5
Figure 6–8: Periphery Clock Networks (EP3SE260 Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Figure 6–9: Periphery Clock Networks (EP3SL340 Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6
Figure 6–10: Stratix III Dual-Regional Clock Region . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-7
Figure 6–11: Clock Input Multiplexer Logic for L2, L3, T1, T2, B1, B2, R2, and R3 PLLs . . . . . . . . . . . . . 6-14
Figure 6–12: Clock Input Multiplexer Logic for L1, L4, R1, and R4 PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14
Figure 6–13: Stratix III Global Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Figure 6–14: Regional Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-15
Figure 6–15: Stratix III External PLL Output Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-16
Figure 6–16: clkena Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
Figure 6–17: clkena Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-17
Figure 6–18: Stratix III PLL Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
Figure 6–19: Stratix III PLL Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21
Figure 6–20: External Clock Outputs for Top/Bottom PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-22
Figure 6–21: External Clock Outputs for Left/Right PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-23
Figure 6–22: Stratix III PLL Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-24
Stratix III Device Handbook, Volume 1
© March 2011 Altera Corporation
Related parts for EP3SL150F1152C3N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
![DK-CYCII-2C20N](/photos/9/20/92074/mfgdk-cycii-2c20nboard_tmb.jpg)
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
![EP610PC-35](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-15](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP610IPC-25](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-30](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-12](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
![EP220PC-10A](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
![P85C224-66](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP320PC](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP2A15B724C7](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
![EP610PC-25T](/images/manufacturer_photos/0/0/41/altera_corporation_tmb.jpg)
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: