EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 161
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Chapter 6: Clock Networks and PLLs in Stratix III Devices
Clock Networks in Stratix III Devices
Table 6–9. Regional Clock Outputs From PLLs on Stratix III Devices
Clock Source Control for PLLs
© July 2010
RCLK[0..11]
RCLK[12..31]
RCLK[32..43]
RCLK[44..63]
RCLK[64..69]
RCLK[70..75]
RCLK[76..81]
RCLK[82..87]
Note to
(1) All PLL counter outputs can drive RCLK networks.
Clock Resource
Table
Altera Corporation
6–9:
Table 6–8. PLL Connectivity to GCLKs on Stratix III Devices (Part 2 of 2)
Table 6–9
The clock input to Stratix III PLLs comes from clock input multiplexers. The clock
multiplexer inputs come from dedicated clock input pins, PLLs through the GCLK
and RCLK networks, or from dedicated connections between adjacent Top/Bottom
and Left/Right PLLs. The clock input sources to Top/Bottom and Left/Right PLLs
(L2, L3, T1, T2, B1, B2, R2, and R3) are shown in
input sources to Left/Right PLLs (L1, L4, R1, and R4) are shown in
The multiplexer select lines are set in the configuration file (SRAM object file [.sof] or
programmer object file [.pof]) only. Once programmed, this block cannot be changed
without loading a new configuration file (.sof or .pof). The Quartus II software
automatically sets the multiplexer select signals depending on the clock sources
selected in the design.
GCLK12
GCLK13
GCLK14
GCLK15
Note to
(1) Only PLL counter outputs C0 - C3 can drive GCLK networks.
Clock Network
L1
—
—
—
—
—
—
—
v
Table
lists how the PLL clock outputs connect to RCLK networks.
v
—
—
—
—
—
—
—
L2
6–8:
v
L3
—
—
—
—
—
—
—
—
—
—
—
L1
L4
—
—
—
—
v
—
—
—
L2
—
—
—
—
v
B1
—
—
—
—
—
—
—
L3
—
—
—
—
L4
—
—
—
—
PLL Number
B2
v
—
—
—
—
—
—
—
(Note 1)
B1
—
—
—
—
R1
—
—
—
—
—
—
v
—
PLL Number
Figure
B2
—
—
—
—
v
R2
—
—
—
—
—
—
—
R1
—
—
—
—
6–11; the corresponding clock
Stratix III Device Handbook, Volume 1
R2
—
—
—
—
R3
—
—
v
—
—
—
—
—
(Note 1)
R3
—
—
—
—
R4
v
—
—
—
—
—
—
—
Figure
R4
—
—
—
—
v
T1
—
—
—
—
—
—
—
6–12.
T1
v
v
v
v
v
T2
—
—
—
—
—
—
—
v
v
v
v
T2
6–13
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