EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 293

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 8: External Memory Interfaces in Stratix III Devices
Chapter Revision History
Chapter Revision History
Table 8–13. Chapter Revision History (Part 1 of 2)
© March 2010 Altera Corporation
March 2010,
version 1.9
May 2009,
version 1.8
February 2009,
version 1.7
October 2008,
version 1.6
July 2008,
version 1.5
May 2008,
version 1.4
Date and Revision
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■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Updated Table 8–1 and Table 8–2.
■
■
■
■
■
■
■
Table 8–13
Added
Updated “DLL”,
sections.
Added
Updated
Added
Updated
Minor text edits.
Updated Table 8–1, Table 8–2, Table 8–3, Table 8–2, Table 8–4, and
Table 8–10.
Updated Figure 8–3, Figure 8–4, Figure 8–5, Figure 8–6, and Figure 8–7.
Updated “DLL”, “Memory Interfaces Pin Support”, and “Rules to
Combine Groups”sections.
Updated Table 8–1,Table 8–2, and Table 8–6.
Updated “Data and Data-Strobe/Clock Pins” section.
Removed “Referenced Document” section.
Updated Table 8–1, Table 8–2, Table 8–3, Table 8–4, Table 8–5,
Table 8–7, and Table 8–8.
Updated the “Rules to Combine Groups”, “Phase Offset Control”, “OCT”,
“Introduction”, “Memory Interfaces Pin Support”, “Combining ×16/×18
DQS/DQ groups for ×36 QDR II+/QDR II SRAM Interface”, “Rules to
Combine Groups”, “DQS Phase-Shift Circuitry”, “DLL”, and “DQS Delay
Chain” sections.
Updated Figure 8–2, Figure 8–4, Figure 8–10, Figure 8–21, and
Figure 8–22.
Updated New Document Format.
Added (Note 3) to Table 8–5.
Updated Figure 8–2, Figure 8–9, Figure 8–18, Figure 8–21, and
Figure 8–22.
Updated Table 8–1, Table 8–2, Table 8–3, Table 8–4, Table 8–7, and
Table 8–10.
Added Table 8–7 and Table 8–8.
Added Figure 8–19.
Added new “Supporting ×36 QDR II+/QDR II SRAM Interfaces in the F780
and F1152-Pin Packages” section.
Updated “Data and Data Clock/Strobe Pins”.
Updated “Referenced Documents”.
“Delay Chain”
Figure
Table 8–11
Figure
Table
lists the revision history for this chapter.
8–22,
8–7.
8–12,
“DQS Logic
and
Figure
section.
Figure
Table
8–23,
Changes Made
Block”, and
8–12.
8–13,and
Figure
Figure
8–24, and
“Dynamic OCT Control”
8–20.
Figure
8–25.
Stratix III Device Handbook, Volume 1
Updated for the
Quartus II software
version 9.1 SP2
release.
Text, Table, and Figure
updates.
Summary of Changes
—
—
—
—
8–45