EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 418

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

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Boundary-Scan Description Language (BSDL) Support
Stratix III Device Handbook, Volume 1
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For more information about boundary scan testing, contact Altera
www.altera.com.
The Boundary-Scan Description Language (BSDL), a subset of VHDL, provides a
syntax that allows you to describe the features of an IEEE Std. 1149.1 BST-capable
device that can be tested. Test software development systems then use the BSDL files
for test generation, analysis, and failure diagnostics.
For more information about BSDL files for IEEE Std. 1149.1-compliant Stratix III
devices, refer to the
To perform BST on a configured device, you will require a post configuration BSDL
file that is customized to your design. This file can be generated with the BSDL
Customizer script.
For more information about the BSDL Customizer, refer to the
page on the Altera website.
Perform a SAMPLE/PRELOAD test cycle prior to the first EXTEST test cycle to
ensure that known data is present at the device pins when you enter the EXTEST
mode. If the OEJ update register contains a 0, the data in the OUTJ update register
is driven out. The state must be known and correct to avoid contention with other
devices in the system.
Do not perform EXTEST testing during ICR. This instruction is supported before
or after ICR, but not during ICR. Use the CONFIG_IO instruction to interrupt
configuration and then perform testing, or wait for configuration to complete.
If performing testing before configuration, hold the nCONFIG pin low.
Stratix III BSDL Files
Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
page on the Altera website.
Boundary-Scan Description Language (BSDL) Support
© July 2010 Altera Corporation
Altera BSDL Support
®
Application at