EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 74
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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3–8
Figure 3–5. M9K RAM Block LAB Row Interface
Stratix III Device Handbook, Volume 1
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
C4 Interconnects
The M144K blocks use eight interfaces in the same device column. The M144K block
local interconnects are driven by R4, C4, and direct link interconnects from adjacent
LABs on either the right or left side of the MRAM block. Up to 20 direct link input
connections to the M144K block are possible from the left adjacent LABs and another
20 possible from the right adjacent LAB. M144K block outputs can also connect to the
LABs on the block’s left and right sides through direct link interconnect.
shows the interface between the M144K RAM block and the logic array.
M9K Local
Interconnect
20
20
datain
control
signals
clocks
LAB Row Clocks
address
M9K
dataout
byte
enable
36
Chapter 3: MultiTrack Interconnect in Stratix III Devices
20
© October 2008 Altera Corporation
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
from adjacent LAB
R4 Interconnects
Memory Block Interface
Figure 3–6
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